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Hi-Fi and Telephony Dual Codec
FEATURES DESCRIPTION
The WM8753L is a low power, high quality stereo Codec with integrated Voice CODEC designed for portable digital telephony applications such as mobile phone, or headset with Hi-Fi playback capability. The device integrates dual interfaces to two differentially connected microphones, and includes drivers for speakers, headphone and earpiece. External component requirements are reduced as no separate microphone or headphone amplifiers are required, and Cap-less connections can be made to all loads. Advanced on-chip digital signal processing performs tone control, Bass Boost and automatic level control for the microphone or line input through the ADC. The two ADCs may be used to support Voice noise cancellation in a partnering DSP, or for stereo recording. The WM8753L Hi-Fi DAC can operate as a master or a slave, with various master clock frequencies including 12 or 24MHz for USB devices, 13MHz or 19.2MHz for cellular systems, or standard 256fs rates like 12.288MHz and 24.576MHz. Internal PLLs generate all required clocks for both Voice and Hi-Fi converters. If audio system clocks already exist, the PLLs may be committed to alternative uses. The WM8753L operates at a nominal supply voltage of 2V, although the digital core can operate at voltages down to 1.42V to save power, and the maximum for all supplies is 3.6 Volts. Different sections of the chip can also be powered down under software control. * *
WM8753L
Hi-Fi DAC: interfaced over I2S type link Audio sample rates: 8, 11.025, 16, 22.05, 24, 32, 44.1, 48, 88.2, 96 * DAC SNR 98dB, THD -84dB (`A' weighted @ 48kHz) * ADC SNR 95dB, THD -82dB (`A' weighted @ 48kHz) * On-chip Headphone Driver with cap-less output option - 40mW output power on 16 / 3.3V - with 16 load: SNR 90dB, THD -75dB - with 10k load: SNR 94dB, THD -90dB * On-chip speaker driver with 0.5W into 8R * Voice Codec: interfaced over Voice interface * supports sample rates from 8ks/s to 48ks/s * ADC and DAC SNR 82dB, THD -74dB * Two Differential Microphone Interfaces - Dual ADCs support noise cancellation in external DSP - Programmable ALC / Noise Gate * Low-noise bias supplied for electret microphones Other features * On-chip PLLs supporting 12, 13, 19.2MHz and other clocks * Cap-less connection options to headphones, earpiece, spkr. * Low power, low voltage - 1.8V to 3.6V (digital core: 1.42V to 3.6V) - power consumption <20mW all-on with 2V supplies - <12mW for PCM CODEC operation * 7x7x0.9mm QFN package, 5x5x0.9mm BGA package
APPLICATIONS
* * MP3 Player / Recorder mobile phone Bluetooth stereo headset
WOLFSON MICROELECTRONICS plc www.wolfsonmicro.com
Advanced Information, June 2004, Rev 3.1 Copyright 2004 Wolfson Microelectronics plc
Advanced Information
WM8753L TABLE OF CONTENTS
DESCRIPTION .......................................................................................................1 FEATURES ............................................................................................................1 APPLICATIONS .....................................................................................................1 TABLE OF CONTENTS .........................................................................................2 PIN CONFIGURATION - QFN................................................................................4 PIN CONFIGURATION - BGA ...............................................................................4 ORDERING INFORMATION ..................................................................................4 PIN DESCRIPTION ................................................................................................5 ABSOLUTE MAXIMUM RATINGS.........................................................................6
SIMULATED THERMAL PROPERTIES......................................................................... 6
RECOMMENDED OPERATING CONDITIONS .....................................................6 ELECTRICAL CHARACTERISTICS ......................................................................7
TERMINOLOGY ............................................................................................................ 9 OUTPUT PGA'S LINEARITY ....................................................................................... 10
SIGNAL TIMING REQUIREMENTS .....................................................................13
SYSTEM CLOCK TIMING ........................................................................................... 13 MODE/GPIO3 AND CSB/GPIO5 LATCH ON POWERUP TIMING .............................. 13 AUDIO INTERFACE TIMING - MASTER MODE......................................................... 14 AUDIO INTERFACE TIMING - SLAVE MODE ............................................................ 15 CONTROL INTERFACE TIMING - 3-WIRE MODE ..................................................... 16 CONTROL INTERFACE TIMING - 2-WIRE MODE ..................................................... 17
DEVICE DESCRIPTION .......................................................................................18
INTRODUCTION ......................................................................................................... 18 INPUT SIGNAL PATH.................................................................................................. 20 MICROPHONE INPUTS ............................................................................................. 24 PGA CONTROL........................................................................................................... 28 AUTOMATIC LEVEL CONTROL (ALC) ....................................................................... 31 3D STEREO ENHANCEMENT .................................................................................... 34 OUTPUT SIGNAL PATH.............................................................................................. 36 ANALOGUE OUTPUTS ............................................................................................... 42 HEADPHONE SWITCH ............................................................................................... 46 HEADPHONE OUTPUT............................................................................................... 47 INTERRUPT CONTROLLER ....................................................................................... 48 GENERAL PURPOSE INPUT/OUTPUT ...................................................................... 51 DIGITAL AUDIO INTERFACES ................................................................................... 53 AUDIO INTERFACES CONTROL................................................................................ 57 CONTROL INTERFACE .............................................................................................. 61 MASTER CLOCK AND PHASE LOCKED LOOP ......................................................... 65 AUDIO SAMPLE RATES ............................................................................................. 68 POWER SUPPLIES ..................................................................................................... 70 POWER MANAGEMENT............................................................................................. 71 REGISTER MAP.......................................................................................................... 74 TERMINOLOGY .......................................................................................................... 77
DAC FILTER RESPONSES .................................................................................78 ADC FILTER RESPONSES .................................................................................79 VOICE FILTER RESPONSES..............................................................................81
VOICE DAC FILTER RESPONSES ............................................................................. 81 VOICE ADC FILTER RESPONSES ............................................................................. 81
DE-EMPHASIS FILTER RESPONSES ................................................................82
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WM8753L
Advanced Information
HIGHPASS FILTER..............................................................................................83 PACKAGE DIAGRAM - 48-PIN QFN ...................................................................85 PACKAGE DIAGRAM - 52-PIN BGA...................................................................86 IMPORTANT NOTICE ..........................................................................................87
ADDRESS: .................................................................................................................. 87
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Advanced Information
WM8753L PIN CONFIGURATION - BGA
PIN CONFIGURATION - QFN
MODE/GPIO3
CSB/GPIO5
MIC2N
MIC1N
GPIO4
VXDIN
SCLK
SDIN
MIC2
MIC1
RXN
48 47 46 45 44 43 42 41 40 39 38 37 VXDOUT VXCLK VXFS LRC BCLK ADCDAT DACDAT MCLK DBVDD DCVDD DGND PCMCLK 1 2 3 4 5 6 36 35 34 33 32 31 LINE2 LINE1 ACOP ACIN MICBIAS VMID VREF AGND AVDD MONO1 MONO2 SPKRVDD
WM8753LEFL
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 GP1/CLK1 GP2/CLK2 LOUT1 HPVDD ROUT1 HP/SPKRGND ROUT2 LOUT2 PGND PVDD OUT4 OUT3 30 29 28 27 26 25
ORDERING INFORMATION
ORDER CODE WM8753LGEFL/V WM8753LGEFL/RV WM8753LEB/V WM8753LEB/RV Note: QFN Reel quantity = 2,200 BGA Reel quantity = 3,500 TEMPERATURE RANGE -25C to +85C -25C to +85C -25C to +85C -25C to +85C PACKAGE 48-pin QFN (7x7x0.9mm) (lead free) 48-pin QFN (7x7x0.9mm) (lead free, tape and reel) 52-pin BGA (5x5x0.9mm) 52-pin BGA (5x5x0.9mm) (tape and reel) MOISTURE SENSITIVITY LEVEL MSL3 MSL3 MSL3 MSL3 PEAK SOLDERING TEMPERATURE 260oC 260oC 240oC 240oC
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WM8753L PIN DESCRIPTION
BGA J2 H3 J3 H4 J4 J5 H5 J6 H6 J7 H7 J8 J9 G8 H9 G9 F9 E9 E8 D9 D8 C9 B9 A9 A8 B7 B6 A6 A5 B5 A4 B4 A3 B3 A2 A1 B1 C2 C1 D2 D1 E2 E1 F1 F2 G1 H1 J1 PIN NO 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 NAME VXDOUT VXCLK VXFS LRC BCLK ADCDAT DACDAT MCLK DBVDD DCVDD DGND PCMCLK GP2/CLK2 GP1/CLK1 PGND PVDD HPVDD OUT4 OUT3 ROUT1 LOUT1 HP/SPKRGND ROUT2 LOUT2 SPKRVDD MONO2 MONO1 AVDD AGND VREF VMID MICBIAS ACIN ACOP LINE1 LINE2 RXP RXN MIC1 MIC1N MIC2 MIC2N GPIO4 MODE/GPIO3 CSB/GPIO5 SDIN SCLK VXDIN TYPE Digital Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Input/Output Digital Output Digital Input Digital Input Supply Supply Supply Digital Input Digital Output Digital Output Supply Supply Supply Analogue Output Analogue Output Analogue Output Analogue Output Supply Analogue Output Analogue Output Supply Analogue Output Analogue Output Supply Supply Reference Reference Analogue Output Analogue Input Analogue Output Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Analogue Input Digital input/Output Digital Input / Output Digital Input / Output Digital Input / Output Digital Input Digital Input Voice ADC Output
Advanced Information
DESCRIPTION Voice codec data clock / ADC frame clock Voice Codec Frame Sync DAC Frame Sync DAC data clock input / output ADC Digital Audio Data Alternative Output DAC Digital Audio Data Input Master Clock Input Digital Buffer Supply (supply for digital I/O buffers) Digital Core Supply (supply for digital logic, except I/O buffers) Digital ground (all digital logic) VOICE codec master clock input (may be looped from PLL output) General Purpose Output 2, usually PLL2 output General Purpose Output 1, usually PLL1 output PLL ground PLL Supply Headphone Supply Analogue Output 4 (Headphone driver) Analogue Output 3 (Headphone driver) Headphone Output Right Headphone Output Left Headphone and Speaker ground Speaker Output Right Speaker Output Left Speaker Supply Mono analogue output 2 Mono analogue output 1 Analogue supply (feeds ADC and DAC) Analogue ground (feeds ADC and DAC) Buffered ADC and DAC Reference voltage Decoupling for ADC and DAC reference voltage Microphone Bias AC coupled input to ALC PGA in record path ALC Mix output Left Channel Input Right Channel input RX mono differential input positive signal RX mono differential input negative signal Mic Pre-amp input 1 Mic Pre-amp 1 common mode or negative input Mic Pre-amp input 2 Mic Pre-amp 2 common mode or negative input GPIO (General Purpose input/output) usually headphone jack insert autodetect with selectable pull-up/pull-down. Control interface Mode select on reset or GPIO3 3-wire MPU Chip Select / 2-wire MPU interface address selection or GPIO5 3-wire MPU Data Input / 2-wire MPU Date Input / Acknowledge 3-wire MPU Clock Input / 2-wire MPU Clock Input VOICE DAC Input
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WM8753L
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical Characteristics at the test conditions specified. ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage of this device. Wolfson tests its package types according to IPC/JEDEC J-STD-020B for Moisture Sensitivity to determine acceptable storage conditions prior to surface mount assembly. These levels are: MSL1 = unlimited floor life at <30C / 85% Relative Humidity. Not normally stored in moisture barrier bag. MSL2 = out of bag storage for 1 year at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. MSL3 = out of bag storage for 168 hours at <30C / 60% Relative Humidity. Supplied in moisture barrier bag. The Moisture Sensitivity Level for each package type is specified in Ordering Information. CONDITION Supply voltages Voltage range digital inputs Voltage range analogue inputs Operating temperature range, TA Storage temperature after soldering Notes: 1. 2. 3. Analogue, PLL and digital grounds must always be within 0.3V of each other. All digital and analogue supplies are completely independent from each other. DCVDD must be less than or equal to AVDD. MIN -0.3V DGND - 0.3V AGND - 0.3V -25C -65C MAX +3.63V DVDD + 0.3V AVDD + 0.3V +85C +150C
SIMULATED THERMAL PROPERTIES
POWER INPUT (WATTS) 1 Watt 0.5 Watt THETA Ja (OC/W) 48.8 48.9 THETA Jc (OC/W) 17.4 18.2 Tj (OC) 73.8 49.4 Tc(OC) 26.5 25.7
RECOMMENDED OPERATING CONDITIONS
PARAMETER Digital supply range (Core) Digital supply range (Buffer) Analogue supplies range PLL supplies range Ground SYMBOL DCVDD DBVDD AVDD PLLVDD DGND,AGND,PLLGND, HP/SPKRGND TEST CONDITIONS MIN 1.42 1.8 1.8 1.8 0 TYP MAX 3.6 3.6 3.6 3.6 UNIT V V V V V
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WM8753L ELECTRICAL CHARACTERISTICS
Advanced Information
Test Conditions DCVDD = 1.5V, AVDD = HPVDD = DBVDD = SPKRVDD = PLLVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Full-scale Input Signal Level (0dB) - note this changes with AVDD Input Capacitance SYMBOL VINFS TEST CONDITIONS MIN TYP 1.0 MAX UNIT V rms Analogue Inputs (LINE1, LINE2, RXP, RXN)
CLINE1/2, RXP/N VINFS
10
pF
Microphone Preamp Inputs (MIC1, MIC1N, MIC2, MIC2N) Full-scale Input Signal Level (0dB) - note this changes with AVDD Mic preamp gain range Mic preamp equivalent input noise Input resistance Input resistance Input resistance Input resistance Input resistance Recommended decoupling cap Input Capacitance Programmable Gain Programmable Gain Step Size Mute Attenuation Automatic Level Control (ALC) Target Record Level Gain Hold Time (Note 1) Gain Ramp-Up (Decay) Time (Note2) Gain Ramp-Down (Attack) Time (Note 2) Signal to Noise Ratio (Note 4, 5) Total Harmonic Distortion (Note 6) Channel Separation (Note 7) Signal to Noise Ratio (Note 4, 5) Total Harmonic Distortion (Note 6) Channel Separation (Note 7) Signal to Noise Ratio (A-weighted) Total Harmonic Distortion (Note 6) SNR THD tHOLD tDCY tATK MCLK = 12.288MHz (Note 3) -28.5 -6 dB ms ms ms 0, 2.67, 5.33, 10.67, ... , 43691 (time doubles with each step) 24, 48, 96, ... , 2458 (time doubles with each step) 6, 12, 24, ... , 6140 (time doubles with each step) A-weighted, 0dB gain full-scale, 0dB gain 1kHz input signal A-weighted, 0dB gain full-scale, 0dB gain 1kHz input signal A-weighted RL = 10 k full-scale signal TBD 95 -82 90 82 -74 90 98 -84 Guaranteed Monotonic At 30dB gain RMIC1N, RMIC2N RMIC1N, RMIC2N RMIC1N, RMIC2N RMIC1N, RMIC2N RMIC1, RMIC2 CDECOUP CMICIN -17.25 0.75 TBD Gain set to 30dB Gain set to 24dB Gain set to 18dB Gain set to 12dB 177 -12 12 TBD 5 10 18 33 163 0.33 10 30 30 mV rms dBV dB uV k k k k k uF pF dB dB dB
Programmable Gain Amplifier (PGA)
LINE1/2 to Analogue to Digital Converter (ADC) dB dB dB dB dB dB dB dB
LINE1/2 to Voice Analogue to Digital Converter (ADC), fs = 8kHz
Digital to Analogue Converter (DAC) to Lineout (LOUT1/2, ROUT1/2, MONO1, MONO2,OUT3 with 10k / 50pF load)
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Advanced Information
WM8753L
Test Conditions DCVDD = 1.5V, AVDD = HPVDD = DBVDD = SPKRVDD = PLLVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNIT Voice Digital to Analogue Converter (DAC) to Lineout (LOUT1/2, ROUT1/2, MONO1, MONO2,OUT3 with 10k / 50pF load), fs = 8kHz Signal to Noise Ratio (A-weighted) Input Resistance SNR RLINE1/2 RRXP RRXN Total Harmonic Distortion (Note 6) Tone Control Bass Boost Bass Boost Step Size Bass Filter Characteristic Treble Boost Treble Boost Step Size Treble Filter Characteristic Output Mixers (Left, Right and Mono mix) PGA gain range into mixer PGA gain step into mixer Analogue Outputs (L/ROUT1, L/ROUT2, MONO1) 0dB full scale output voltage Programmable Gain range Programmable Gain step size Mute Attenuation Channel Separation Headphone Output (LOUT1/2, OUT3) Total Harmonic Distortion THD HPVDD=1.8V, RL=32 Po = 5mW HPVDD=1.8V, RL=16 Po = 5mW HPVDD=3.3V, RL=32 Po = 20mW HPVDD=3.3V, RL=16 Po = 20mW Signal to Noise Ratio (A-weighted) Speaker Output (L/ROUT2) Total Harmonic Distortion THD Po=180mW, RL=8, SPKRVDD=3.3V Po=400mW, RL=8, SPKRVDD=3.3V Signal to Noise Ratio (A-weighted) SNR SPKRVDD=3.3V, RL=8 SPKRVDD=2.5V, RL=8 -50 0.3 -40 1 90 90 dB % dB % dB dB SNR HPVDD = 3.3V HPVDD = 1.8V 90 90 0.013 -78 0.013 - 78 0.01 -80 0.01 -80 % dB % dB % dB % dB dB dB 1kHz signal monotonic 1kHz, full scale signal -73 1 85 90 AVDD/3.3 +6 Vrms dB dB dB dB -15 3 +6 dB dB -6 -6 0 1.5dB 2nd order 0 1.5dB 2nd order +9 dB dB +9 dB dB THD RL = 10 k full-scale signal A-weighted LINE1/2 input to output mixer, gain = +6dB TBD 10 30 20 -74 82 dB k k k dB
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WM8753L
Advanced Information
Test Conditions DCVDD = 1.5V, AVDD = HPVDD = DBVDD = SPKRVDD = PLLVDD = 3.3V, TA = +25oC, 1kHz signal, fs = 48kHz, 24-bit audio data unless otherwise stated. PARAMETER Microphone Bias Bias Voltage (MBVSEL=0) Bias Voltage (MBVSEL=1) Bias Current Source Output Noise Voltage Input HIGH Level Input LOW Level Output HIGH Level Output LOW Level GPIO4 Input Input HIGH Level Input LOW Level VIH VIL 1.4 0.8 V V VMICBIAS VMICBIAS IMICBIAS Vn VIH VIL VOH VOL IOL=1mA IOH-1mA 0.9xDBVDD 0.1xDBVDD 1K to 20kHz 0.7xDBVDD 0.3xDBVDD 15 -3% -3% 0.9*AVDD 0.75*AVDD +3*% +3*% 3 V V mA nV/Hz V V V V SYMBOL TEST CONDITIONS MIN TYP MAX UNIT
Digital Input / Output (excluding GPIO4)
TERMINOLOGY
1. 2. 3. 4. 5. Hold Time is the length of time between a signal detected being too quiet and beginning to ramp up the gain. It does not apply to ramping down the gain when the signal is too loud, which happens without a delay. Ramp-up and Ramp-Down times are defined as the time it takes for the PGA to sweep across 90% of its gain range. All hold, ramp-up and ramp-down times scale proportionally with MCLK Signal-to-noise ratio (dB) - SNR is a measure of the difference in level between the full scale output and the output with no signal applied. (No Auto-zero or Automute function is employed in achieving these results). Dynamic range (dB) - DR is a measure of the difference between the highest and lowest portions of a signal. Normally a THD+N measurement at 60dB below full scale. The measured signal is then corrected by adding the 60dB to it. (e.g. THD+N @ -60dB= -32dB, DR= 92dB). THD+N (dB) - THD+N is a ratio, of the rms values, of (Noise + Distortion)/Signal. Channel Separation (dB) - Also known as Cross-Talk. This is a measure of the amount one channel is isolated from the other. Normally measured by sending a full scale signal down one channel and measuring the other.
6. 7.
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WM8753L
OUTPUT PGA'S LINEARITY
10.000 0.000 Output PGA Gains -10.000 Measured Gain [dB] -20.000 -30.000 -40.000 -50.000 -60.000 -70.000 40 50 60 70 80 90 100 110 120 130 XXXVOL Register Setting (binary) LOUT1 ROUT1 LOUT2 ROUT2 MONOOUT
2.000 1.750 Output PGA Gain Step Size 1.500 1.250 1.000 0.750 LOUT1 0.500 0.250 0.000 40 50 60 70 80 90 100 110 120 130 ROUT1 LOUT2 ROUT2 MONOOUT
Step Size [dB]
XXXVOL Register Setting (binary)
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WM8753L POWER CONSUMPTION
The power consumption of the WM8753L depends on the following factors.
Advanced Information
Supply voltages: Reducing the supply voltages also reduces supply currents, and therefore results in significant power savings. Operating mode: Power consumption is lower in mono modes than in stereo, as one ADC / DAC / PGA is switched OFF. It is also reduced when the device is used for playback only (ADC off) or for recording only (DAC off). Unused outputs should be switched off (for example, when line out is not used, do not enable the LINE outputs). Headphone volume: At high volume, the power dissipated in the headphone itself is greater than the power consumption of the WM8753L. High headphone volume also increases the power consumption of the on-chip headphone drivers.
MODE DESCRIPTION MIN All active (PCM, Stereo Mic, Stereo H/P Playback) Headphone Playback Only Line-Out Playback Only Line Record Only (0dB gain) Mic Record Only (29dB gain boost, ALC active) Standby Table 1 Power Consumption
POWER CONSUMPTION TYP 32 36 36 34 39 1.65 MAX UNITS mW mW mW mW mW mW
Notes: 1. 2. 3. 4. AVDD, HPVDD, DBVDD, DCVDD = 3.3V, TA = +25oC, fs = 48kHz All channels are stereo. All figures are quiescent, with no signal. The power dissipated in the headphone itself is not included in the above table.
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WM8753L
Table 2 Power Consumption Figures
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WM8753L SIGNAL TIMING REQUIREMENTS
SYSTEM CLOCK TIMING
tMCLKL MCLK tMCLKH tMCLKY
Advanced Information
Figure 1 System Clock Timing Requirements Test Conditions CLKDIV2=0, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock cycle time MCLK duty cycle TMCLKY TMCLKDS 54 60:40 40:60 ns SYMBOL MIN TYP MAX UNIT
Test Conditions CLKDIV2=1, DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MCLK System clock pulse width high MCLK System clock pulse width low MCLK System clock cycle time TMCLKL TMCLKH TMCLKY 10 10 27 ns ns ns SYMBOL MIN TYP MAX UNIT
MODE/GPIO3 AND CSB/GPIO5 LATCH ON POWERUP TIMING
tdbpu
DBVDD
AVDD/DCVDD
Power-on-Reset (internal)
MODE/GPIO3
CSB/GPIO5 tpusetup tpuhold
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Advanced Information
WM8753L
Test Conditions DCVDD = 1.42V, DBVDD = AVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC, Slave Mode fs = 48kHz, MCLK = 384fs, 24-bit data, unless otherwise stated. PARAMETER System Clock Timing Information MODE/GPIO3 and CSB/GPIO5 to AVDD and DCVDD power-up setup time AVDD and DCVDD to MODE/GPIO3 and CSB/GPIO5 hold time DBVDD powerup to DCVDD or AVDD powerup Note: 1. DBVDD must be supplied before or at same time as either DCVDD or AVDD to ensure MODE and CSB are defined internally when power on reset is released tpusetup tpuhold tdbpu 100 1 0 us ms us SYMBOL MIN TYP MAX UNIT
AUDIO INTERFACE TIMING - MASTER MODE
Figure 2 Digital Audio Data Timing - Master Mode (see Control Interface) Test Conditions DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information LRC / VXFS propagation delay from BCLK / VXCLK falling edge ADCDAT / VXDOUT propagation delay from BCLK / VXCLK falling edge DACDAT / VXDIN setup time to BCLK / VXCLK rising edge DACDAT / VXDIN hold time from BCLK / VXCLK rising edge tDL tDDA tDST tDHT 10 10 10 10 ns ns ns ns SYMBOL MIN TYP MAX UNIT
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AUDIO INTERFACE TIMING - SLAVE MODE
Advanced Information
Figure 3 Digital Audio Data Timing - Slave Mode Test Conditions DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Audio Data Input Timing Information BCLK / VXCLK cycle time BCLK / VXCLK pulse width high BCLK / VXCLK pulse width low LRC / VXFS set-up time to BCLK / VXCLK rising edge LRC / VXFS hold time from BCLK / VXCLK rising edge DACDAT / VXDIN hold time from BCLK / VXCLK rising edge ADCDAT / VXDOUT propagation delay from BCLK / VXCLK falling edge Note: 1. BCLK / VXCLK period should always be greater than or equal to MCLK / VXCLK period. tBCY tBCH tBCL tLRSU tLRH tDH tDD 50 20 20 10 10 10 10 ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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Advanced Information
WM8753L
tCSL CSB tSCY tSCH SCLK tSCL tSCS tCSS tCSH
CONTROL INTERFACE TIMING - 3-WIRE MODE
SDIN tDSU SDOUT tDD tDHO
LSB
LSB
Note: SDOUT is not an external pin. For data readback SDOUT may be selected to be ADCDAT, GP1, GP2, GPIO3 or GPIO4
Figure 4 Control Interface Timing - 3-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK rising edge to CSB rising edge SCLK pulse cycle time SCLK pulse width low SCLK pulse width high SDIN to SCLK set-up time SCLK to SDIN hold time CSB pulse width low CSB pulse width high CSB rising to SCLK rising SCLK falling to SDOUT propagation delay Pulse width of spikes that will be suppressed tSCS tSCY tSCL tSCH tDSU tDHO tCSL tCSH tCSS tDD tps 5 80 200 80 80 40 40 40 40 40 10 ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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CONTROL INTERFACE TIMING - 2-WIRE MODE
t3 SDIN t4 t6 SCLK t1 t9 t7 t2 t5 t3
Advanced Information
t8
Figure 5 Control Interface Timing - 2-Wire Serial Control Mode Test Conditions DCVDD = 1.42V, DBVDD = AVDD = HPVDD = SPKRVDD = PLLVDD = 3.3V, DGND = AGND = PLLGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs, 24-bit data, unless otherwise stated. PARAMETER Program Register Input Information SCLK Frequency SCLK Low Pulse-Width SCLK High Pulse-Width Hold Time (Start Condition) Setup Time (Start Condition) Data Setup Time SDIN, SCLK Rise Time SDIN, SCLK Fall Time Setup Time (Stop Condition) Data Hold Time Pulse width of spikes that will be suppressed t1 t2 t3 t4 t5 t6 t7 t8 t9 tps 0 600 900 5 0 600 1.3 600 600 100 300 300 400 kHz ns us ns ns ns ns ns ns ns ns SYMBOL MIN TYP MAX UNIT
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Advanced Information
WM8753L
DEVICE DESCRIPTION
INTRODUCTION
The WM8753L is a low power audio codec combining a high quality stereo audio DAC with a high quality stereo ADC and mono DAC. The stereo ADC may be configured for operation as a mono or stereo voice ADC to operate with the mono DAC as a voice codec. Alternatively the ADC may be configured as a hi-fi ADC for high quality record function. In voice mode the ADC filters are optimised for voice record function. Applications for such a combined device include MP3 playing `smartphones' and Bluetooth connected high quality stereo headsets. The mono voice codec might be used either for the usual voice codec function, or perhaps as an additional codec for support of Bluetooth links from such MP3 phones. Alternatively, if not required for such functions, the ADC of the codec may be reconfigured so it is clocked off the I2S audio data interface domain, and its output sent over the Hi-Fi audio interface as well as the voice audio interface, so it might be used as a recording ADC in an I2S based audio system.
FEATURES
The chip offers great flexibility in use, and so can support many different modes of operation as follows:
LINE INPUTS
The device includes two pairs of stereo analogue inputs that can be switched internally. LINE1 and LINE2 can be used as either a pair of mono line level inputs, or as a single stereo pair. They may also be used as differential input or be mixed together. A further two inputs, RXP and RXN, can be used as a single differential input or mixed together. The output from these inputs can be played back in stereo form to the headphones, or mono form to the transmit mono output. The mono output supports both single ended and differential output, using a pair of output pins. If not required, the differential output buffer may be powered down.
MICROPHONE INPUTS
Two microphone preamplifiers are provided, allowing for a pair of external microphones to be differentially connected, with user defined gain using internal resistors, offering gain range from +12dB to +30dB. Alternatively, three microphones can be connected to one microphone preamplifier, with the second preamplifier disabled, and the microphone required is then selected. A microphone bias is output from the chip which can be used to bias all microphones. The signal routing can be configured to allow manual adjustment of mic levels, or indeed to allow the ALC loop to control the level of mic signal that is transmitted.
PGA AND ALC OPERATION
A programmable gain amplifier is provided in the input path to the ADC. This may be used manually or in conjunction with a mixed analog/digital automatic level control (ALC) which keeps the recording volume constant.
HI-FI DAC
The hi-fi DAC provides high quality audio playback suitable for all portable audio hi-fi type applications, including MP3 players and portable disc players of all types.
VOICE CODEC
The on-chip stereo ADC and mono DAC are of a high quality using a multi-bit high-order oversampling architecture to deliver optimum performance with low power consumption. Various sample rates are supported, from the 8ks/s rate typically used in voice codecs, up to the 48ks/s rate used in high quality audio applications. The ADC digital filters may be switched for voice mode to filters with steeper roll-off.
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OUTPUT MIXERS
Advanced Information Flexible mixing is provided on the outputs of the device; a stereo mixer is provided for the stereo headphone or line outputs, and an additional mono mixer for the mono output to the transmit side of the equipment. Gain adjustment capability, and signal switching is provided to allow for all possible signal combinations; eg. Sidetone, transmission of stereo music playback along with voice, whilst at the same time as listening to music, and received phone call if so desired. The output buffers can be configured in several ways, allowing support of up to three sets of external transducers; ie stereo headphone, BTL speaker, and BTL earpiece may be connected simultaneously. (thermal implications should be considered before simultaneous full power operation of all outputs is attempted!) Alternatively, if a speaker output is not required, the LOUT2 and ROUT2 pins might be used as a stereo speaker or headphone driver, (disable output invert buffer on ROUT2). In that case either two sets of headphones might be driven, or the LOUT2 and ROUT2 pins used as a line output driver. The Earpiece may be driven in BTL mode, with the ROUT1 signal inverted into the OUT3 pin, or alternatively OUT3 may be either the mono version of ROUT1 and LOUT1, or simply a buffered version of the chip midrail reference voltage. This voltage may then be used as a headphone `pseudo ground' allowing removal of the large AC coupling capacitors often used in the output path.
AUDIO INTERFACES
The WM8753L has a pair of audio interfaces, to support the Hi-Fi DAC and the PCM codec. The Hi-Fi DAC is supported with a 4 wire standard audio DAC interface which supports a number of audio data formats including I2S, DSP Mode (a burst mode in which frame sync plus 2 data packed words are transmitted), MSB-First, left justified and MSB-First, right justified, and can operate in master or slave modes. The PCM codec is connected via standard PCM type interface, comprising a frame sync, FS, a bitclk VXCLK, (typically 16 clocks per frame), and a pair of data lines for DAC input and ADC output data. A master clock for the PCM codec (typically 256fs or 2.048MHz when running at 8ks/s) may also be supplied as an input, if the system controller can provide this, to PCMCLK input pin. In the event of the system controller not being able to provide this clock, it may be generated in the WM8753L using PLL2. Note that the MCLK input to the chip must be present for PLL2 to operate, as it is a digital PLL type of circuit and uses this high speed master clock. In the event of the PCM codec not being required, (temporarily or otherwise) the ADC output data may be sent over the hi-fi audio interface using the ADCDAT line. In this case the ADC may be configured to run at the same sample rate as the hi-fi DAC and use the same clock signals (BCLK and LRC). It may also be configured to run at a different sample rate and instead use the FS and VXCLK as the ADC data frame sync and clock. Both interfaces may be configured to run in Master mode when LRC, BCLK, FS and VXCLK are outputs from the WM8753L. A mixed Master-Slave mode is also supported allowing BCLK / VXCLK to be outputs from the WM8753L and LRC / FS to be inputs.
CONTROL INTERFACES
To allow full software control over all its features, the WM8753L offers a choice of 2 or 3 wire MPU control interface. It is fully compatible and an ideal partner for a wide range of industry standard microprocessors, controllers and DSPs. Selection between the modes is via the MODE/GPIO3 pin. In 2 wire mode only slave operation is supported and the address of the device may be selected between two values using the CSB/GPIO5 pin. The interface mode and 2-wire address select are set on power-up by the sampling of the MODE/GPIO3 and CSB/GPIO5 pins by the power-on reset. This allows these pins to be used as GPIO pins after powerup.
CLOCKING SCHEMES
WM8753L offers the normal audio DAC clocking scheme operation, where 256 or 384fs or higher MCLK is provided to the DAC. Similarly the PCM codec can be operated in normal PCM type mode where a 256fs clock is sent along with the PCM frame clock and data. However, a pair of PLLs are also included which may be used to generate these clocks in the event that they are not available from the system controller. The first PLL1 uses an input clock, typically the Rf reference clock used in most mobile systems, to generate high quality audio clocks. The second PLL2 can use this same reference clock. If these PLLs are not required for generation of these clocks, they can be reconfigured to generate alternative clocks which may then be output and used elsewhere in the system. The WM8753L can also generate standard audio clock rates from a 12 or 24MHz USB clock without the use of the PLLs.
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Advanced Information
WM8753L
POWER CONTROL
The design of the WM8753L has given much attention to power consumption without compromising performance. It operates at very low voltages, and includes the ability to power off any unused parts of the circuitry under software control, and includes standby and power off modes.
OPERATION SCENARIOS
Flexibility in the design of the WM8753L allows for a wide range of operational scenarios, some of which are proposed below: Telephony with MP3 playback: The voice codec may be used as standard voice codec, and the stereo DAC used for MP3 type playback. The user may choose to transmit the mono version of the MP3 playback to the Tx side of the phone conversation as required. Recording of the phone conversation would then require to be supported in the digital domain, after the voice codec. (digital Tx and Rx sides of the conversation would need to be digitally summed as required). Telephony with recording: In many smart-phone applications the voice codec for voice conversion will be included in the cellphone base-band chipset. In such cases the analog (often differential) mic input and speaker outputs from this voice codec will be routed to the WM8753L line or mic inputs, and mono outputs. The WM8753L will then provide the buffers to connect to the system transducers (speakers, mics, headphones etc.) and also the stereo hi-fi DAC and mixers to allow MP3 type playback. The ADC may then be used for recording the phone conversation, both Tx and Rx parts, and the extra DAC might be used for generation of confirmation tones or ringtones as required. Bluetooth Hi-Fi stereo headset; In Bluetooth headsets a mono PCM codec is required for the standard telephony quality voice channel. But for the support of compressed hi-fi quality stereo, a hi-fi quality stereo DAC is required. In this case WM8753L can supply both these needs. The BTL speaker driver could be recommitted as either stereo headphone driver, or stereo speaker driver, and perhaps the other headphone output re-used as stereo line output. Analog FM tuner support: An analog stereo FM tuner might be connected to the Line inputs of WM8753, and the stereo signal listened to via headphones, or transmitted over the `phone.
INPUT SIGNAL PATH
The WM8753L has a combination of analogue inputs, microphone preamps, mixers and switches allowing flexibility in the configuration of the input to left and right ADCs and to analogue bypass paths into the Left, Right and Mono output Mixers. The input to the ADC may be routed through a PGA whose gain is controlled either by the user or by the on-chip ALC function (see Automatic Level Control). The ADCs may be powered off independently and a single ADC may be used for left and right ADC input mono mixing.
SIGNAL INPUTS
The WM8753L has three sets of high impedance, low capacitance AC coupled differential inputs as well as two high impedance, low capacitance AC coupled mono line inputs. Two of the differential inputs (MICIN1/MICIN1N and MICIN2/MICIN2N) have a microphone pre-amp and selectable gain of +12dB to +30dB in 6dB steps. RXN and RXP are a differential line input and can also be configured as a stereo to mono mix input. In addition there are two mono LINE inputs (LINE1 and LINE2) which can be used as a single stereo input. The LINE1 and LINE2 inputs may be configured as a differential input or a stereo to mono mix using the Line input mixer under the control of register bits LMSEL. The LMSEL bits also allow either one of the inputs to be enabled and the other disabled. The Line mixer output may then be routed to the ALC mixer by setting LINEALC and/or to the output Mono mixer via the bypass path. The Line mixer has -6dB of gain so that a 0dB signal on LINE1 and LINE2 will sum to give a 0dB signal at the mixer output. There is an analogue input to analogue output bypass path into the Left, Right and Mono output mixers. The Left bypass path may be selected to be either the output of the RX mixer or the LINE1 input under the control of LM. The Right bypass path may be selected to be either the output of the RX mixer or the LINE2 input under the control of RM. The Mono bypass path may be selected to be either the output of the Line mixer or the RX mixer under the control of MM.
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Advanced Information RXN and RXP are inputs to a mixer controlled by the RXMSEL register bits. By default this is a differential input (RXP-RXN). The RX mixer can also be configured as a stereo to mono mix input (RXP+RXN). Alternatively RXP or RXN can be individually selected as mono inputs with the other input disabled. The RX mixer has -6dB of gain so that a 0dB signal on RXP and RXN will sum to give a 0dB signal at the mixer output. In addition there is a Sidetone path from the Mic Mux to the left, right and mono mixers. This Sidetone path may be selected to be the output from the left or right ADC input PGA, the Mic1 preamp or the Mic2 preamp under the control of MICMUX[1:0]. The Left ADC input is selected using LADCSEL[1:0]. It can be selected to be i) a direct analogue input from LINE1 or the output of the RX mixer block; ii) through the input PGA and ALC mixer; iii) DC measurement input from LINE1. For direct analogue input the input may be selected from either LINE1 or the RX mixer using LM. The ALC mixer may be used to mix MIC1, MIC2, LINE and RX differential inputs, selected using MIC1ALC, MIC2ALC, LINEALC and RXALC. The Right ADC input is selected using RADCSEL[1:0]. It can be selected to be i) a direct analogue input from LINE2 or the RX mixer input; ii) through the input PGA from the MIC2 preamp; iii) Record mixer output. For direct analogue input the input may be selected from either LINE2 or the RX mixer using RM. The Record mixer may be used to mix the output from the left, right and mono output mixers, e.g. for recording a phone call. The inputs to the Record mixer are selected using LSEL, RSEL and MSEL and have independent input gain control from -15dB to +6dB. The input to the Left ADC PGA via the external dc blocking capacitor is from the output of the ALC mixer, which allows the mixing of the output from the Line mixer, the RX mixer, the Mic1 preamp and the Mic2 preamp under the control of LINEALC, RXALC, MIC1ALC and MIC2ALC. The signal inputs are biased internally to the reference voltage VREF. Whenever the analogue inputs are muted or the device placed into standby mode, the inputs are kept biased to VREF using special anti-thump circuitry. This reduces any audible clicks that may otherwise be heard when changing inputs.
DC MEASUREMENT
For DC measurements (for example, battery voltage monitoring), the input signal at the LINE1 input can be taken directly into the left ADC, bypassing the PGA. The ADC output then becomes unsigned relative to AVDD, instead of being a signed (two's complement) number relative to VREF. The input range for dc measurement is AGND to AVDD. The ADC high pass filter should be disabled when measuring DC voltages. REGISTER ADDRESS R46 (2Eh) ADC input Mode BIT [3:2] LABEL RADCSEL[1:0] DEFAULT 00 DESCRIPTION Right ADC Input Select 00 : PGA 01 : LINE2 or RXP-RXN 10 : Left + Right + Mono output Mix 11 : unused Left ADC Input Select 00 : PGA 01 : LINE1 or RXP-RXN 10 : LINE1 DC measurement 11 : unused
[1:0]
LADCSEL[1:0]
00
Table 3 ADC Input Control
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WM8753L
REGISTER ADDRESS R47 (2Fh) Input Control (1) BIT [4:3] LABEL LMSEL[1:0] DEFAULT 00 DESCRIPTION Line Mix Select: 00: LINE1 + LINE2 01: LINE1 - LINE2 10: LINE1 (LINE2 disconnected) 11: LINE2 (LINE1 disconnected) Mono Mux Select 0 : Line Mix Output 1: Rx Mix output ( RXP +/- RXN ) Right Mux Select 0 : LINE2 1 : Rx Mix output ( RXP +/- RXN ) Left Mux Select 0 : LINE1 1 : Rx Mix output ( RXP +/- RXN )
2
MM
0
1
RM
0
0
LM
0
Table 4 Input and Bypass Mux Control
REGISTER ADDRESS R48 (30h) Input Control (2)
BIT [7:6]
LABEL RXMSEL[1:0]
DEFAULT 00
DESCRIPTION Differential input, Rx, mixer 00: RXP - RXN 01: RXP + RXN 10: RXP (RXN disconnected) 11: RXN (RXP disconnected) Mic Mux Sidetone Select 00 : Sidetone = Left PGA output 01 : Sidetone = Mic 1 preamp output 10 : Sidetone = Mic 2 preamp output 11 : Sidetone = Right PGA output ALC Mix input select Line Mix 0 : Line Mix not selected into ALC Mix 1 : Line Mix selected into ALC Mix ALC Mix input select MIC2 0 : MIC2 not selected into ALC Mix 1 : MIC2 selected into ALC Mix ALC Mix input select MIC1 0 : MIC1 not selected into ALC Mix 1 : MIC1 selected into ALC Mix ALC Mix input select RX 0 : RX not selected into ALC Mix 1 : RX selected into ALC Mix
[5:4]
MICMUX[1:0]
00
3
LINEALC
0
2
MIC2ALC
0
1
MIC1ALC
0
0
RXALC
0
Table 5 ALC Mix and Mic Mux Input Select
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REGISTER ADDRESS R32 (20h) Record Mix (1) BIT 7 LABEL RSEL DEFAULT 0
Advanced Information
DESCRIPTION Record Mixer Select Right Mix 0 : Right Mix not selected into Record mixer 1 : Right mix selected into Record mixer Right mixer signal to Record mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Record Mixer Select Left Mix 0 : Left Mix not selected into Record mixer 1 : Left mix selected into Record mixer Left mixer signal to Record mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Record Mixer Select Mono Mix 0 : Mono Mix not selected into Record mixer 1 : Mono mix selected into Record mixer Mono mixer signal to Record mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB
6:4
RRECVOL [2:0]
101 (0dB)
3
LSEL
0
2:0
LRECVOL[2:0]
101 (0dB)
R33 (21h) Record Mix (2)
3
MSEL
0
2:0
MRECVOL [2:0]
101
Table 6 Record Mixer Input Select and Gain Control MONO MIXING The stereo ADC can operate as a stereo or mono device, or the two channels can be mixed to mono, either in the analogue domain (in the front end of the ADC) or in the digital domain (after the ADC). MONOMIX selects the mode of operation. For analogue mono mix either the left or right channel ADC can be used, allowing the unused ADC to be powered off or used for a dc measurement conversion. The user also has the flexibility to select the data output from the audio interface using DATSEL. The default is for left and right channel ADC data to be output, but the interface may also be configured so that e.g. left channel ADC data is output as both left and right data for when an analogue mono mix is selected. Note: If DC measurement is selected this overrides the MONOMIX selection. REGISTER ADDRESS R46 (2Eh) ADC input Mode Table 7 Mono Mixing BIT 5:4 LABEL MONOMIX[1:0] DEFAULT 00 DESCRIPTION 00: Stereo 01: Analogue Mono Mix (using left ADC) 10: Analogue Mono Mix (using right ADC) 11: Digital Mono Mix
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Advanced Information
WM8753L
REGISTER ADDRESS R2 (02h) Additional Control (1) BIT 8:7 LABEL DATSEL [1:0] DEFAULT 00 DESCRIPTION 00: left data = left ADC; right data = right ADC 01: left data = left ADC; right data = left ADC 10: left data = right ADC; right data = right ADC 11: left data = right ADC; right data = left ADC
Table 8 ADC Data Output Configuration
MICROPHONE INPUTS
MIC1N micamp1 MIC1 amp1out
MICAMP1EN
vmid vmid
MIC2N/ MIC3 micamp2 MIC2 amp2out
MICAMP2EN
vmid vmid
Figure 6 Internal Microphone Input Circuit There are two microphone pre-amplifiers which can be configured in a variety of ways to accommodate up to 3 single ended or 2 differential microphone inputs. The microphone input circuit is shown in Figure 6. Each microphone preamplifier has a separate enable bit, MICAMP1EN and MICAMP2EN. The gain for each preamp can be set independently using MIC1BOOST and MIC2BOOST. REGISTER ADDRESS R21 (15h) BIT 8 LABEL MICAMP1EN DEFAULT 0 DESCRIPTION Microphone amplifier 1 enable 0 = Mic1 amp disabled 1 = Mic1 amp enabled Microphone amplifier 2 enable 0 = Mic2 amp disabled 1 = Mic2 amp enabled
7
MICAMP2EN
0
Table 9 Mic Preamp Enables
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REGISTER ADDRESS R47 (2Fh) Mic Input Boost BIT [8:7] LABEL MIC2BOOST[1:0] DEFAULT 00
Advanced Information
DESCRIPTION MIC2 Preamp Gain Control 00 : +12dB 01 : +18dB 10 : +24dB 11 : +30dB MIC1 Preamp Gain Control 00 = +12dB 01 = +18dB 10 = +24dB 11 = +30dB
[6:5]
MIC1BOOST[1:0]
00
Table 10 MIC Preamp Gain Control The suggested configuration for the external microphone circuit is shown in Figure 7.
Figure 7 Suggested External Microphone Input Configuration
DIFFERENTIAL OPERATION
It is possible to connect up to two mics differentially. Microphone1 is connected between the MIC1 and MIC1N inputs and microphone2 is connected between the MIC2 and MIC2N inputs. It should be noted that in differential mode, with mic inputs routed to the ADCs, an extra invert occurs in the MIC1 (left ADC) path due to the extra mixer. This can be compensated for by inverting the left ADC signal back again using ADCPOL.
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WM8753L
REGISTER ADDRESS R2 (02h) ADC control BIT [6:5] LABEL ADCPOL[1:0] DEFAULT 00 DESCRIPTION 00 = Polarity not inverted 01 = L polarity invert 10 = R polarity invert 11 = L and R polarity invert
Table 11 ADC Polarity Control
SINGLE ENDED OPERATION
It is possible to connect up to three microphones single endedly. Microphone1 is connected to the MIC1 input , microphone2 to the MIC2 input, microphone3 to the MIC2N input and MIC1N is connected to Vref. The gains, MIC1BOOST and MIC2BOOST, should be set to be identical and micamp2 must be disabled. Any of the three microphones can then be selected as the output from micamp1 using MICSEL. REGISTER ADDRESS R51 (33h) Mic Select BIT [7:6] LABEL MICSEL[1:0] DEFAULT 00 DESCRIPTION Microphone selected 00 : MIC1 01 : MIC2 10 : MIC3 11 : unused
Table 12 MIC Select Control
MICROPHONE BIASING CIRCUIT
The MICBIAS output provides a low noise reference voltage suitable for biasing electret type microphones and the associated external resistor biasing network. Refer to the Applications Information section for recommended external components. The MICBIAS voltage can be altered via the MBVSEL register bit. When MBVSEL=0, MICBIAS=0.9*AVDD and when MBVSEL=1, MICBIAS=0.75*AVDD. The output can be enabled or disabled using the MICB control bit (see also the "Power Management" section). REGISTER ADDRESS R20 (14h) Power Management (1) 5 BIT LABEL MICB DEFAULT 0 DESCRIPTION Microphone Bias Enable 0 = OFF (high impedance output) 1 = ON
Table 13 Microphone Bias Control
REGISTER ADDRESS R51 (33h) Mic bias comp control 8
BIT
LABEL MBVSEL
DEFAULT 0
DESCRIPTION Microphone Bias Voltage Control 0 = 0.9 * AVDD 1 = 0.75 * AVDD
Table 14 Microphone Bias Voltage Control The internal MICBIAS circuitry is shown in Figure 8. Note that the maximum source current capability for MICBIAS is 3mA. The external biasing resistors therefore must be large enough to limit the MICBIAS current to 3mA.
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Advanced Information
VMID internal resistor
MB
MBVSEL=0 MICBIAS = 1.8 x VMID = 0.9 X AVDD MBVSEL=1 MICBIAS = 1.5 x VMID = 0.75 X AVDD
internal resistor
AGND
Figure 8 Microphone Bias Schematic
MICBIAS CURRENT DETECT
The WM8753L includes a microphone bias current detect circuit which allows the user to set thresholds for the microphone bias current, above which an interrupt will be triggered. There are two separate interrupt bits, MICDET to allow the user to e.g. distinguish between one or two microphones connected to the WM8753L, and MICSHT to detect a shorted microphone (mic button press). The thresholds for the microphone bias current are set by MBTHRESH[2:0], for MICDET, and MBSCTHRESH[1:0] for MICSHT. Thresholds for each code are shown in Table 15. The circuit is enabled by setting MBCEN. See the GPIO and Interrupt Controller sections for details on the interrupt and status readback for the microphone bias current detect. REGISTER ADDRESS R51 (33h) BIT 5:4 LABEL MBSCTHRESH DEFAULT 00 DESCRIPTION Microphone Bias, Shorted Current Threshold Select 00: 500uA 01: 1000uA 10: 1600uA 11: 2300uA These values are for 3.3V supply and scale with supply voltage. Microphone Bias, Current Threshold Select 000:250uA 001:410uA ....160uA steps up to 111:1370uA These values are for 3.3V supply and scale with supply voltage. Mic Bias Current Comparator Circuit enable 0 : Comparator disabled 1 : Comparator enabled
3:1
MBTHRESH
000
0
MBCEN
0
Table 15 Mic Bias Current Comparator Circuit Control
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WM8753L
The PGA matches the input signal level to the ADC input range. The PGA gain is logarithmically adjustable from -17.25dB to +30dB in 0.75dB steps. Each PGA can be controlled either by the user or by the ALC function (see Automatic Level Control). When ALC is enabled for one or both channels, then writing to the corresponding PGA control register has no effect. The gain is independently adjustable on both Right and Left Line Inputs. However, by setting the LRINBOTH or RLINBOTH bits whilst programming the PGA gain, both channels are simultaneously updated. This reduces the required number of software writes required. Setting the LZCEN and RZCEN bits enables a zero-cross detector which ensures that PGA gain changes only occur when the signal is at zero, eliminating any zipper noise. If zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. This function may be enabled by setting TOEN in register R18 (12h). The inputs can also be muted in the analogue domain under software control. The software control registers are shown in Table 16 REGISTER ADDRESS R49 (31h) Left Channel PGA 8 BIT LABEL LIVU 0 DEFAULT DESCRIPTION Left Volume Update 0 = Store LINVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LINVOL, right = intermediate latch) Left Channel Input Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: LIVU must be set to un-mute. Left Channel Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately Left Channel Input Volume Control 111111 = +30dB 111110 = +29.25dB . . 0.75dB steps down to 000000 = -17.25dB Right Volume Update 0 = Store RINVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (right = RINVOL, left = intermediate latch) Right Channel Input Analogue Mute 1 = Enable Mute 0 = Disable Mute Note: RIVU must be set to un-mute. Right Channel Zero Cross Detector 1 = Change gain on zero cross only 0 = Change gain immediately Right Channel Input Volume Control 111111 = +30dB 111110 = +29.25dB . . 0.75dB steps down to 000000 = -17.25dB Timeout Enable 0 : Timeout Disabled 1 : Timeout Enabled
PGA CONTROL
7
LINMUTE
1
6
LZCEN
0
5:0
LINVOL [5:0]
010111 ( 0dB )
R50 (32h) Right Channel PGA
8
RIVU
0
7
RINMUTE
1
6
RZCEN
0
5:0
RINVOL [5:0]
010111 ( 0dB )
R18 (12h) Additional Control
0
TOEN
0
Table 16 Input PGA Software Control
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ANALOGUE TO DIGITAL CONVERTER (ADC)
Advanced Information
The WM8753L uses a multi-bit, oversampled sigma-delta ADC for each channel. The use of multi-bit feedback and high oversampling rates reduces the effects of jitter and high frequency noise. The ADC Full Scale input level is proportional to AVDD. With a 3.3V supply voltage, the full scale level is 1.0 Volts r.m.s. Any voltage greater than full scale may overload the ADC and cause distortion.
ADC DIGITAL FILTER
The ADC filters perform true 24 bit signal processing to convert the raw multi-bit oversampled data from the ADC to the correct sampling frequency to be output on the digital audio interface. The digital filter path is illustrated in Figure 9.
FROM ADC
DIGITAL DECIMATOR
DIGITAL FILTER
DIGITAL HPF
TO DIGITAL AUDIO INTERFACE
ADCHPD
Figure 9 ADC Digital Filter The characteristic of the digital decimation filter is selectable using control bit VXFILT for HiFi and voice modes of operation. In Voice mode the filter has a steeper roll-off and reduced stopband attenuation. The ADC digital filters also contain a digital high pass filter, selectable via software control. The cut-off frequency of the highpass filter is selectable to suit the mode of operation. For HiFi record mode the default cut-off of 3.4Hz (at fs=48kHz) is recommended and for voice record a cut-off of 100Hz or 200Hz (at fs=8kHz) may be selected The frequency response of the highpass filter will scale with sample rate so the 100Hz cut-off at 8KHz sample rate will scale to a 200Hz cut-off at 16kHz sample rate. The decimation and high-pass filter responses are detailed in the Digital Filter Characteristics section. When the high-pass filter is enabled the dc offset is continuously calculated and subtracted from the input signal. By setting HPOR, the last calculated dc offset value is stored and will continue to be subtracted from the input signal. If the DC offset is changed, the stored and subtracted value will not change unless HPOR is reset. This feature can be used for calibration purposes.
HPMODE fs=8kHz 00 01 10 11 0.6 41 82 170
Cut-off (Hz) fs=16kHz 1.1 82 164 340 fs=48kHz 3.7 246 492 1020
Table 17 Highpass Filter Cut-off Frequencies The output data format can be programmed by the user to accommodate stereo or monophonic recording on both inputs. The polarity of the output signal can also be changed under software control. The software control is shown in Table 18.
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Advanced Information
WM8753L
REGISTER ADDRESS R2 (02h) ADC Control BIT 6:5 LABEL ADCPOL [1:0] DEFAULT 00 DESCRIPTION 00 = Polarity not inverted 01 = L polarity invert 10 = R polarity invert 11 = L and R polarity invert ADC Filter Select 0 = HiFi Filter 1 = Voice FIlter ADC High pass Filter Cut-off Select 00 = 3.4Hz @ fs = 48kHz 01 = 82Hz @ fs = 16kHz (41Hz @ fs = 8kHz) 10 = 82Hz @ fs = 8kHz (164Hz @ fs = 16kHz) 11 = 170Hz @ fs = 8kHz (340Hz @ fs = 16kHz) Store dc offset 1 = store offset 0 = clear offset ADC High Pass Filter Enable (Digital) 1 = Disable High Pass Filter 0 = Enable High Pass Filter
4
VXFILT
0
3:2
HPMODE
00
1
HPOR
0
0
ADCHPD
0
Table 18 ADC Signal Path Control
DIGITAL ADC VOLUME CONTROL
The output of the ADCs can be digitally amplified or attenuated over a range from -97dB to +30dB in 0.5dB steps. The volume of each channel can be controlled separately. The gain for a given eight-bit code X is given by: 0.5 x (X-195) dB for 1 X 255; MUTE for X = 0
The LAVU and RAVU control bits control the loading of digital volume control data. When LAVU or RAVU are set to 0, the LADCVOL or RADCVOL control data will be loaded into the respective control register, but will not actually change the digital gain setting. Both left and right gain settings are updated when either LAVU or RAVU are set to 1. This makes it possible to update the gain of both channels simultaneously.
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REGISTER ADDRESS R16(10h) Left ADC Digital Volume BIT 7:0 LABEL LADCVOL [7:0] DEFAULT 11000011 ( 0dB )
Advanced Information
DESCRIPTION Left ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -97dB 0000 0010 = -96.5dB ... 0.5dB steps up to 1111 1111 = +30dB Left ADC Volume Update 0 = Store LADCVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LADCVOL, right = intermediate latch) Right ADC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -97dB 0000 0010 = -96.5dB ... 0.5dB steps up to 1111 1111 = +30dB Right ADC Volume Update 0 = Store RADCVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = RADCVOL)
8
LAVU
0
R17 (11h) Right ADC Digital Volume
7:0
RADCVOL [7:0]
11000011 ( 0dB )
8
RAVU
0
Table 19 ADC Digital Volume Control
AUTOMATIC LEVEL CONTROL (ALC)
The WM8753L has an automatic level control that aims to keep a constant recording volume irrespective of the input signal level. This is achieved by continuously adjusting the PGA gain so that the signal level at the ADC input remains constant. A digital peak detector monitors the ADC output and changes the PGA gain if necessary.
input signal
PGA gain
signal after ALC
ALC target level
hold time
decay time
attack time
Figure 10 ALC Operation
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WM8753L
The ALC function is enabled using the ALCSEL control bits. When enabled, the recording volume can be programmed between -6dB and -28.5dB (relative to ADC full scale) using the ALCL register bits. An upper limit for the PGA gain can be imposed by setting the MAXGAIN control bits. HLD, DCY and ATK control the hold, decay and attack times, respectively: Hold time is the time delay between the peak level detected being below target and the PGA gain beginning to ramp up. It can be programmed in power-of-two (2n) steps, e.g. 2.67ms, 5.33ms, 10.67ms etc. up to 43.7s. Alternatively, the hold time can also be set to zero. The hold time only applies to gain ramp-up, there is no delay before ramping the gain down when the signal level is above target. Decay (Gain Ramp-Up) Time is the time that it takes for the PGA gain to ramp up across 90% of its range (e.g. from -15B up to 27.75dB). The time it takes for the recording level to return to its target value therefore depends on both the decay time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the decay time. The decay time can be programmed in power-of-two (2n) steps, from 24ms, 48ms, 96ms, etc. to 24.58s. Attack (Gain Ramp-Down) Time is the time that it takes for the PGA gain to ramp down across 90% of its range (e.g. from 27.75dB down to -15B gain). The time it takes for the recording level to return to its target value therefore depends on both the attack time and on the gain adjustment required. If the gain adjustment is small, it will be shorter than the attack time. The attack time can be programmed in power-of-two (2n) steps, from 6ms, 12ms, 24ms, etc. to 6.14s. When operating in stereo, the peak detector takes the maximum of left and right channel peak values, and any new gain setting is applied to both left and right PGAs, so that the stereo image is preserved. However, the ALC function can also be enabled on one channel only. In this case, only one PGA is controlled by the ALC mechanism, while the other channel runs independently with its PGA gain set through the control register. When one ADC channel is unused or used for DC measurement, the peak detector disregards that channel. The ALC function can also operate when the two ADC outputs are mixed to mono in the digital domain, but not if they are mixed to mono in the analogue domain, before entering the ADCs. ALCSR is used to set the sample rate for the ALC when the ADC is in voice mode (SRMODE=1). When ALC is enabled in voice mode the ALCSR bits should be set to match the ADC sample rate as shown in Table 20.
ADC SAMPLE RATE 8kHz 11.025/12kHz 16kHz 22.05kHz 32kHz 48/44/1kHz 88.2/96kHz Table 20 ADC Sample Rate
ALCSR [3:0] 0110 1000 1010 1010 1100 0000 1110
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REGISTER ADDRESS R12 (0Ch) ALC Control 1 BIT 8:7 LABEL ALCSEL [1:0] DEFAULT 00 (OFF)
Advanced Information
DESCRIPTION ALC function select 00 = ALC off (PGA gain set by register) 01 = Right channel only 10 = Left channel only 11 = Stereo (PGA registers unused) Set Maximum Gain of PGA 111 : +30dB 110 : +24dB ....(-6dB steps) 001 : -6dB 000 : -12dB ALC target - sets signal level at ADC input 0000 = -28.5dB FS 0001 = -27.0dB FS ... (1.5dB steps) 1110 = -7.5dB FS 1111 = -6dB FS ALC uses zero cross detection circuit. ALC sample rate control (only used when in PCM mode, otherwise SR[4:0] bits control the sample rate) ALC hold time before gain is increased. 0000 = 0ms 0001 = 2.67ms 0010 = 5.33ms ... (time doubles with every step) 1111 = 43.691s ALC decay (gain ramp-up) time 0000 = 24ms 0001 = 48ms 0010 = 96ms ... (time doubles with every step) 1010 or higher = 24.58s ALC attack (gain ramp-down) time 0000 = 6ms 0001 = 12ms 0010 = 24ms ... (time doubles with every step) 1010 or higher = 6.14s
6:4
MAXGAIN [2:0]
111 (+30dB)
3:0
ALCL [3:0]
1011 (-12dB)
R13 (0Dh) ALC Control 2
8 7:4
ALCZC ALCSR[3:0]
0 (zero cross off) 0000
3:0
HLD [3:0]
0000 (0ms)
R14 (0Eh) ALC Control 3
7:4
DCY [3:0]
0011 (192ms)
3:0
ATK [3:0]
0010 (24ms)
Table 21 ALC Control
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PEAK LIMITER
To prevent clipping when a large signal occurs just after a period of quiet, the ALC circuit includes a limiter function. If the ADC input signal exceeds 87.5% of full scale (-1.16dB), the PGA gain is ramped down at the maximum attack rate (as when ATK = 0000), until the signal level falls below 87.5% of full scale. This function is automatically enabled whenever the ALC is enabled. Note: 1. If ATK = 0000, then the limiter makes no difference to the operation of the ALC. It is designed to prevent clipping when long attack times are used.
NOISE GATE
When the signal is very quiet and consists mainly of noise, the ALC function may cause "noise pumping", i.e. loud hissing noise during silence periods. The WM8753L has a noise gate function that prevents noise pumping by comparing the signal level at the LINPUT1/2/3 and/or RINPUT1/2/3 pins against a noise gate threshold, NGTH. The noise gate cuts in when: Signal level at ADC [dB] < NGTH [dB] + PGA gain [dB] + Mic Boost gain [dB] This is equivalent to: Signal level at input pin [dB] < NGTH [dB] The ADC output can then either be muted or alternatively, the PGA gain can be held constant (preventing it from ramping up as it normally would when the signal is quiet). The table below summarises the noise gate control register. The NGTH control bits set the noise gate threshold with respect to the ADC full-scale range. The threshold is adjusted in 1.5dB steps. Levels at the extremes of the range may cause inappropriate operation, so care should be taken with set-up of the function. Note that the noise gate only works in conjunction with the ALC function, and always operates on the same channel(s) as the ALC (left, right, both, or none). REGISTER ADDRESS R15 (0Fh) Noise Gate Control BIT 7:3 LABEL NGTH [4:0] DEFAULT 00000 DESCRIPTION Noise gate threshold 00000 -76.5dBfs 00001 -75dBfs ... 1.5 dB steps 11110 -31.5dBfs 11111 -30dBfs Noise gate type 0 = PGA gain held constant 1 = mute ADC output Noise gate function enable 1 = enable 0 = disable
1
NGG
0
0
NGAT
0
Table 22 Noise Gate Control
3D STEREO ENHANCEMENT
The WM8753L has a digital 3D enhancement option to artificially increase the separation between the left and right channels. This effect can be used for recording or playback, but not for both simultaneously. Selection of 3D for record or playback is controlled by register bit MODE3D. Switching the 3D filter from record to playback or from playback to record may only be done when ADC and DAC are disabled. The WM8753L control interface will only allow MODE3D to be changed when ADC and DAC are disabled (ie ADCL = 0, ADCR = 0, DACL = 0 and DACR = 0). The 3D enhancement function is activated by the 3DEN bit, and has two programmable parameters. The DEPTH3D setting controls the degree of stereo expansion. Additionally, one of four filter characteristics can be selected for the 3D processing, using the 3DFILT control bits.
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REGISTER ADDRESS R19 (13h) 3D enhance 7 BIT LABEL MODE3D DEFAULT 0
Advanced Information
DESCRIPTION Playback/Record 3D select 0 = 3D selected for Record 1 = 3D selected for Playback Upper Cut-off frequency 0 = High (2.2kHz at 48kHz sampling) 1 = Low (1.5kHz at 48kHz sampling) Lower Cut-off frequency 0 = Low (200Hz at 48kHz sampling) 1 = High (500Hz at 48kHz sampling) Stereo depth 0000: 0% (minimum 3D effect) 0001: 6.67% .... 1110: 93.3% 1111: 100% (maximum 3D effect) 3D function enable 1: enabled 0: disabled
6
3DUC
0
5
3DLC
0
4:1
DEPTH3D[3:0]
0000
0
3DEN
0
Table 23 3D Stereo Enhancement Function When 3D enhancement is enabled (and/or the tone control for playback) it may be necessary to attenuate the signal by 6dB to avoid limiting. This is a user selectable function, enabled by setting ADCDIV2 for the record path and DACDIV2 for the playback path.
REGISTER ADDRESS R18 (012h) ADC and DAC control 2
BIT
LABEL ADCDIV2
DEFAULT 0
DESCRIPTION ADC 6dB attenuate enable 0 = disabled (0dB) 1 = -6dB enabled DAC 6dB attenuate enable 0 = disabled (0dB) 1 = -6dB enabled
1
DACDIV2
0
Table 24 ADC and DAC 6dB Attenuation Select
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The WM8753L output signal paths consist of digital filters, a stereo Hi-Fi DAC, Voice DAC, analogue mixers and output drivers. The digital filters and DACs are enabled when the WM8753L is in `playback only' or `record and playback' mode. The mixers and output drivers can be separately enabled by individual control bits (see Analogue Outputs). Thus it is possible to utilise the analogue mixing and amplification provided by the WM8753L, irrespective of whether the DACs are running or not. The WM8753L Hi-Fi DAC receives digital input data on the DACDAT pin. The digital filter block processes the data to provide the following functions: Digital volume control Graphic equaliser and Dynamic Bass Boost Sigma-Delta Modulation Two high performance sigma-delta audio DACs convert the digital data into two analogue signals (left and right).
OUTPUT SIGNAL PATH
The WM8753L Voice DAC receives digital input data on the VXDIN pin which is processed and upsampled by the digital filters and then sigma delta modulated to provide the analogue voice signal. The analogue output from the stereo Hi-Fi DAC and the Voice DAC can then be mixed with each other and the analogue signals from the analogue inputs. The mix is fed to the output drivers, LOUT1/ROUT1, LOUT2/ROUT2, OUT3, OUT4, MONO1 and MONO2. LOUT1/ROUT1: can drive a 16 or 32 stereo headphone or stereo line output. OUT3: can drive a 16 or 32 headphone or line output or buffered Vmid LOUT2/ROUT2: can drive a 16 or 32 stereo headphone or stereo line output, or an 8 mono speaker. MONO1 and MONO2: can drive a mono line output or other load down to 10k OUT4: can drive a 16 or 32 headphone or line output or buffered Vmid.
DIGITAL HI-FI DAC VOLUME CONTROL
The signal volume from each Hi-Fi DAC can be controlled digitally. The gain and attenuation range is -127dB to 0dB in 0.5dB steps. The level of attenuation for an eight-bit code X is given by: 0.5 x (X-255) dB for 1 X 255; MUTE for X = 0
The LDVU and RDVU control bits control the loading of digital volume control data. When LDVU or RDVU are set to 0, the LDACVOL or RDACVOL control data is loaded into an intermediate register, but the actual gain does not change. Both left and right gain settings are updated simultaneously when either LDVU or RDVU are set to 1.
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REGISTER ADDRESS R8 (08h) Left Channel Digital Volume BIT 8 LABEL LDVU DEFAULT 0
Advanced Information
DESCRIPTION Left DAC Volume Update 0 = Store LDACVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LDACVOL, right = intermediate latch) Left DAC Digital Volume Control 0000 0000 = Digital Mute 0000 0001 = -127dB 0000 0010 = -126.5dB ... 0.5dB steps up to 1111 1111 = 0dB Left DAC Volume Update 0 = Store RDACVOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = RDACVOL) Right DAC Digital Volume Control similar to LDACVOL
7:0
LDACVOL [7:0]
11111111 ( 0dB )
R9 (09h) Right Channel Digital Volume
8
RDVU
0
7:0 Table 25 Digital Volume Control
RDACVOL [7:0]
11111111 ( 0dB )
GRAPHIC EQUALISER
The WM8753L has a digital graphic equaliser and adaptive bass boost function. This function operates on digital audio data before it is passed to the audio DACs. Bass enhancement can take two different forms: Linear bass control: bass signals are amplified or attenuated by a user programmable gain. This is independent of signal volume, and very high bass gains on loud signals may lead to signal clipping. * Adaptive bass boost: The bass volume is amplified by a variable gain. When the bass volume is low, it is boosted more than when the bass volume is high. This method is recommended because it prevents clipping, and usually sounds more pleasant to the human ear. Treble control applies a user programmable gain, without any adaptive boost function. Bass and treble control are completely independent with separately programmable gains and filter characteristics. The selectable cut-offs scale with sample frequency to give the following cut-off frequencies at different sample rates BC[2:0] 000 001 010 011 100 101 CUT-OFF AT FS=8KHZ 22Hz 33.3Hz 50Hz 66.7Hz 100Hz 200Hz CUT-OFF AT FS=16KHZ 44Hz 66.7Hz 100Hz 133.3Hz 200Hz 400Hz CUT-OFF AT FS=48KHZ 130Hz 200Hz 300Hz 400Hz 600Hz 1200Hz *
Table 26 Bass Filter Cut-off Frequencies for Different Frequencies
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WM8753L
REGISTER ADDRESS R10 (0Ah) Bass Control 7 BIT LABEL BB 0 DEFAULT DESCRIPTION Bass Boost 0 = Linear bass control 1 = Adaptive bass boost Bass Filter Characteristic - cut-off: 000 = 130Hz at fs = 48kHz 001 = 200Hz at fs = 48kHz 010 = 100Hz at fs = 16kHz 011 = 400Hz at fs = 48kHz 100 = 100Hz at fs = 8kHz 101 = 200Hz at fs = 8kHz Bass Intensity Code 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 R11 (0Bh) Treble Control 6 TC 0 BB=0 +9dB +9dB +7.5dB +6dB +4.5dB +3dB +1.5dB 0dB -1.5dB -3dB -4.5dB -6dB -6dB -6dB -6dB Bypass (OFF) BB=1 15 (max) 14 13 12 11 10 9 8 7 6 5 4 3 2 1
6:4
BC[2:0]
000
3:0
BASS [3:0]
1111 (Disabled)
Treble Filter Characteristic 0 = High Cutoff (8kHz at 48kHz sampling) 1 = Low Cutoff (4kHz at 48kHz sampling) Treble Intensity 0000 or 0001 = +9dB 0010 = +7.5dB ... (1.5dB steps) 1011 to 1110 = -6dB 1111 = Disable
3:0
TRBL [3:0]
1111 (Disabled)
Table 27 Graphic Equaliser
HI-FI DIGITAL TO ANALOGUE CONVERTER (DAC)
After passing through the graphic equaliser filters, digital `de-emphasis' can be applied to the audio data if necessary (e.g. when the data comes from a CD with pre-emphasis used in the recording). Deemphasis filtering is available for sample rates of 48kHz, 44.1kHz and 32kHz. The WM8753L also has a Soft Mute function, which gradually attenuates the volume of the digital signal to zero. When removed, the gain will ramp back up to the digital gain setting. This function is enabled by default. To play back an audio signal, it must first be disabled by setting the DACMU bit to zero.
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REGISTER ADDRESS R1 (01h) DAC Control BIT 2:1 LABEL DEEMP [1:0] DEFAULT 00
Advanced Information
DESCRIPTION De-emphasis Control 11 = 48kHz sample rate 10 = 44.1kHz sample rate 01 = 32kHz sample rate 00 = No De-emphasis Digital Soft Mute 1 = mute 0 = no mute (signal active)
3
DACMU
1
Table 28 HiFi DAC Control The digital audio data is converted to oversampled bit streams in the on-chip, true 24-bit digital interpolation filters. The bitstream data enters two multi-bit, sigma-delta DACs, which convert them to high quality analogue audio signals. The multi-bit DAC architecture reduces high frequency noise and sensitivity to clock jitter. It also uses a Dynamic Element Matching technique for high linearity and low distortion. In normal operation, the left and right channel digital audio data is converted to analogue in two separate DACs. There is also a mono-mix mode where the two audio channels are mixed together digitally, controlled by the DMONOMIX register bits which allow the digital mono mix to be applied to left, right or both DAC channels. If only one DAC channel is being used for the mono mix the other can be powered down. The DAC output defaults to non-inverted. Setting DACINV will invert the DAC output phase on both left and right channels. REGISTER ADDRESS R1 (01h) DAC Control BIT 5:4 LABEL DMONOMIX [1:0] DEFAULT 00 DESCRIPTION DAC Mono Mix 00: stereo 01: mono ((L+R)/2) into DACL, `0' into DACR 10: mono ((L+R)/2) into DACR, `0' into DACL 11: mono ((L+R)/2) into DACL and DACR DAC Phase Invert 0 : non-inverted 1 : inverted
6
DACINV
0
Table 29 HiFi DAC Mono Mix and Phase Invert Select
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WM8753L
OUTPUT MIXERS
The WM8753L provides the option to mix the Hi-FI DAC output signals and Voice DAC output signal with analogue line-in signals from the bypass and sidetone paths. The level of the mixed-in signals can be controlled with PGAs (Programmable Gain Amplifiers). The Mono mixer has a gain of -6dB to allow two signals with input amplitude of 0dB to be mixed together without clipping. This may be compensated for using the output PGAs if required. REGISTER ADDRESS R47 (2Fh) Input Control (1) BIT [4:3] LABEL LMSEL[1:0] DEFAULT 00 DESCRIPTION Line Mix Select: 00: LINE1 + LINE2 01: LINE1 - LINE2 10: LINE1 (LINE2 disconnected) 11: LINE2 (LINE1 disconnected) Mono Mux Select 0 : Line Mix Output 1: Rx Mix output ( RXP +/- RXN ) Right Mux Select 0 : LINE2 1 : Rx Mix output ( RXP +/- RXN ) Left Mux Select 0 : LINE1 1 : Rx Mix output ( RXP +/- RXN )
2
MM
0
1
RM
0
0
LM
0
Table 30 Analogue Input to Output Mixer Bypass Signal Selection (same as Table 4)
REGISTER ADDRESS R48 (30h) Input Control (2)
BIT [7:6]
LABEL RXMSEL[1:0]
DEFAULT 00
DESCRIPTION Differential input, Rx, mixer 00: RXP - RXN 01: RXP + RXN 10: RXP (RXN disconnected) 11: RXN (RXP disconnected) Mic Mux Sidetone Select 00 : Sidetone = Left PGA output 01 : Sidetone = Mic1 preamp output 10 : Sidetone = Mic 2 preamp output 11 : Sidetone = Right PGA output ALC Mix input select Line Mix 0 : Line Mix not selected into ALC Mix 1 : Line Mix selected into ALC Mix ALC Mix input select MIC2 0 : MIC2 not selected into ALC Mix 1 : MIC2 selected into ALC Mix ALC Mix input select MIC1 0 : MIC1 not selected into ALC Mix 1 : MIC1 selected into ALC Mix ALC Mix input select RX 0 : RX not selected into ALC Mix 1 : RX selected into ALC Mix
[5:4]
MICMUX[1:0]
00
3
LINEALC
0
2
MIC2ALC
0
1
MIC1ALC
0
0
RXALC
0
Table 31 Analogue input to output Mixers Sidetone Signal Selection
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REGISTER ADDRESS R34 (22h) Left Mixer Control (1) 8 BIT LABEL LD2LO DEFAULT 0
Advanced Information
DESCRIPTION Left DAC to Left Mixer 0 = Disable (Mute) 1 = Enable Path LM Signal to Left Mixer 0 = Disable (Mute) 1 = Enable Path LM Signal to Left Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Voice DAC to Left Mixer 0 = Disable (Mute) 1 = Enable Path Sidetone Signal to Left Mixer 0 = Disable (Mute) 1 = Enable Path Sidetone Signal to Left Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Voice DAC Signal to Left Mixer Volume 000 = +9dB ... (3dB steps) 111 = -12dB
7
LM2LO
0
6:4
LM2LOVOL [2:0]
101 (-9dB)
R35 (23h) Left Mixer Control (2)
8
VXD2LO
0
7
ST2LO
0
[6:4]
ST2LOVOL [2:0]
101 (-9dB)
[2:0]
VXD2LOVOL
101 (-6dB)
Table 32 Left Output Mixer Control REGISTER ADDRESS R36 (24h) Right Mixer Control (1) 8 BIT LABEL RD2RO DEFAULT 0 DESCRIPTION Right DAC to Right Mixer 0 = Disable (Mute) 1 = Enable Path RM Signal to Right Mixer 0 = Disable (Mute) 1 = Enable Path RM Signal to Right Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Voice DAC to Right Mixer 0 = Disable (Mute) 1 = Enable Path Sidetone Signal to Right Mixer 0 = Disable (Mute) 1 = Enable Path Sidetone Signal to Right Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Voice DAC Signal to Right Mixer Volume 000 = +9dB ... (3dB steps) 111 = -12dB
7
RM2RO
0
[6:4]
RM2ROVOL [2:0]
101 (-9dB)
R37 (25h) Right Mixer Control (2)
8
VXD2RO
0
7
ST2RO
0
[6:4]
ST2ROVOL [2:0]
101 (-9dB)
[2:0]
VXD2ROVOL [2:0]
101 (-6dB)
Table 33 Right Output Mixer Control
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WM8753L
REGISTER ADDRESS R38 (26h) Mono Mixer Control (1) 8 BIT LABEL LD2MO 0 DEFAULT DESCRIPTION Left DAC to Mono Mixer 0 = Disable (Mute) 1 = Enable Path MM Signal to Mono Mixer 0 = Disable (Mute) 1 = Enable Path MM Signal to Mono Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Right DAC to Mono Mixer 0 = Disable (Mute) 1 = Enable Path Sidetone Signal to Mono Mixer 0 = Disable (Mute) 1 = Enable Path Sidetone Signal to Mono Mixer Volume 000 = +6dB ... (3dB steps) 111 = -15dB Voice DAC to Mono Mixer 0 = Disable (Mute) 1 = Enable Path Voice Signal to Mono Mixer Volume 000 = +9dB ... (3dB steps) 111 = -12dB
7
MM2MO
0
[6:4]
MM2MOVOL [2:0]
101 (-9dB)
R39 (27h) Mono Mixer Control (2)
8
RD2MO
0
7
ST2MO
0
[6:4]
ST2MOVOL [2:0]
101 (-9dB)
3
VXD2MO
0
[2:0]
VXD2MOVOL [2:0]
101 (-6dB)
Table 34 Mono Output Mixer Control
ANALOGUE OUTPUTS
LOUT1/ROUT1 OUTPUTS
The LOUT1 and ROUT1 pins can drive a 16 or 32 headphone or a line output (see Headphone Output and Line Output sections, respectively). The signal volume on LOUT1 and ROUT1 can be independently adjusted under software control by writing to LOUT1VOL and ROUT1VOL, respectively. Note that gains over 0dB may cause clipping if the signal is large. Any gain setting below 0101111 (-73dB) mutes the output driver. The corresponding output pin remains at the same DC level (the reference voltage on the VREF pin), so that no click noise is produced when muting or un-muting. A zero cross detect on the analogue output may also be enabled when changing the gain setting to minimize audible clicks and zipper noise as the gain updates. If zero cross is enabled a timeout is also available to update the gain if a zero cross does not occur. This function may be enabled by setting TOEN in register R18 (12h).
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REGISTER ADDRESS R40 (28h) LOUT1 Volume 8 BIT LABEL LO1VU DEFAULT 0
Advanced Information
DESCRIPTION Left Volume Update 0 = Store LOUT1VOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = LOUT1VOL, right = intermediate latch) Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately LOUT1 Volume 1111111 = +6dB ... (1.0 dB steps) 0110000 = -73dB 0101111 to 0000000 = Analogue MUTE Right Volume Update 0 = Store ROUT1VOL in intermediate latch (no gain change) 1 = Update left and right channel gains (left = intermediate latch, right = ROUT1VOL) Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately ROUT1 Volume Similar to LOUT1VOL
7
LO1ZC
0
6:0
LOUT1VOL [6:0]
1111001 (0dB)
R41 (29h) ROUT1 Volume
8
RO1VU
0
7
RO1ZC
0
6:0
ROUT1VOL [6:0]
1111001
Table 35 LOUT1/ROUT1 Volume Control
LOUT2/ROUT2 OUTPUTS
The LOUT2 and ROUT2 output pins are essentially similar to LOUT1 and ROUT1, but they are independently controlled and can also drive an 8 mono speaker (see Speaker Output section). For speaker drive, the ROUT2 signal must be inverted (ROUT2INV = 1), so that the left and right channel are mixed to mono in the speaker [L-(-R) = L+R]. REGISTER ADDRESS R42 (2Ah) LOUT2 Volume BIT 6:0 7 LABEL LOUT2VOL [6:0] LO2ZC DEFAULT 1111001 (0dB) 0 DESCRIPTION Same as LOUT1VOL Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately Same as LO1VU Same as ROUT1VOL Left zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately Same as RO1VU ROUT2 Invert 0 = No Inversion (0 phase shift) 1 = Signal inverted (180 phase shift)
8 R43 (2Bh) ROUT2 Volume 6:0 7
LO2VU ROUT2VOL [6:0] RO2ZC
0 1111001 (0dB) 0
8 R45 (2Dh) Output Control 2
RO2VU ROUT2INV
0 0
Table 36 LOUT2/ROUT2 Volume Control
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Advanced Information
WM8753L
MONO1 OUTPUT
The MONO1 pin can drive a mono line output. The signal volume on MONO1 can be adjusted under software control by writing to MONO1VOL. REGISTER ADDRESS R44 (2Ch) MONOOUT Volume BIT 6:0 LABEL MONO1VOL [6:0] DEFAULT 1111001 (0dB) DESCRIPTION MONO1 Volume 1111111 = +6dB ... (1.0 dB steps) 0110000 = -73dB 0101111 to 0000000 = Analogue MUTE MONO1 zero cross enable 1 = Change gain on zero cross only 0 = Change gain immediately
7
MOZC
0
Table 37 MONO1 Volume Control
MONO2
The MONO2 pin can drive a mono line output and may be configured to output either an inverted MONO1 output, the output from the left or right mixer or a mono mix of the left and right mixer outputs. REGISTER ADDRESS R45 (2Dh) Output Control BIT 8:7 LABEL MONO2SW[1:0] DEFAULT 00 DESCRIPTION MONO2 Output Select 00 = inverted MONO1 01 = Left Mix / 2 10 = Right Mix / 2 11 = (Left Mix + Right Mix ) / 2
Table 38 MONO2 Output Select
OUT3 OUTPUT
The OUT3 pin can drive a 16 or 32 headphone or a line output or be used as a DC reference for a headphone output (see Headphone Output section). It can be selected to either drive out an inverted ROUT2 or mono mix of the left and right mixers for e.g. an earpiece drive between OUT3 and LOUT1 or differential output between OUT3 and MONOOUT. This output is enabled by setting bit OUT3. OUT3SW[1:0] selects the mode of operation required. REGISTER ADDRESS R45 (2Dh) Output Control BIT 1:0 LABEL OUT3SW [1:0] DEFAULT 00 DESCRIPTION OUT3 select 00 = VREF 01 = ROUT2 signal (volume controlled by ROUT2VOL) 10 = (Left Mixer + Right Mixer) / 2 11 = unused
Table 39 OUT3 Select
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OUT4 OUTPUT
Advanced Information
The OUT4 output can be used to output a buffered Vmid for driving a mono or stereo headset in capless mode, output the signal from the record mixer or drive out an inverted LOUT2 signal. The output mode is determined by OUT4SW[1:0]. This output is enabled by setting register bit OUT4 high. REGISTER ADDRESS R63 (3Fh) Additional Control BIT 8:7 LABEL OUT4SW [1:0] DEFAULT 00 DESCRIPTION OUT4 Output select 00 = VREF 01 = Record Mixer 10 = LOUT2 signal (volume controlled by LOUT2VOL) 11 = unused
Table 40 OUT4SW control of OUT4
ZERO CROSS TIMEOUT
A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output pgas the gain will automatically update after a timeout period if a zero cross has not occurred. This is enabled by setting TOEN. The timeout period is dependent on the clock input to the digital and is equal to 221 * input clock period. The timeout clock may be set to be derived from either the mclk or pcmclk using SLWCLK.. REGISTER ADDRESS R18 (12h) Additional Control R52 (34h) Clock Control 0 BIT LABEL TOEN 0 DEFAULT DESCRIPTION Timeout clock enable 0 = timeout clock disabled 1 = timeout clock enabled Timeout and Headphone switch clock source 0 = mclk 1 = pcm clk
0
SLWCLK
0
Table 41 Timeout Clock Controls
ENABLING THE OUTPUTS
Each analogue output of the WM8753L can be separately enabled or disabled. The analogue mixer associated with each output is powered on or off along with the output pin. All outputs are disabled by default. To save power, unused outputs should remain disabled. Outputs can be enabled at any time, except when VREF is disabled (VR=0), as this may cause pop noise (see "Power Management" and "Applications Information" sections) REGISTER ADDRESS R22 (16h) Power Management (3) 8 7 6 5 4 3 2 1 Table 42 Analogue Output Control BIT LABEL LOUT1 ROUT1 LOUT2 ROUT2 OUT3 OUT4 MONO1 MONO2 0 0 0 0 0 0 0 0 DEFAULT DESCRIPTION LOUT1 Enable ROUT1 Enable LOUT2 Enable ROUT2 Enable OUT3 Enable OUT4 Enable MONO1 Enable MONO2 Enable
Note: All "Enable" bits are 1 = ON, 0 = OFF
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Advanced Information
WM8753L
Whenever an analogue output is disabled, it remains connected to VREF (pin 20) through a resistor. This helps to prevent pop noise when the output is re-enabled. The resistance between VREF and L/ROUT1, L/ROUT2 and MONO1 can be controlled using the VROI bit in register 27. The default is low (500), so that any capacitors on the outputs can charge up quickly at start-up. If a high impedance is desired for disabled outputs, VROI can then be set to 1, increasing the resistance to about 90k. REGISTER ADDRESS R45 (2Dh) Additional (1) 3 BIT LABEL VROI 0 DEFAULT DESCRIPTION VREF to analogue output resistance 0: 500 1: 90 k
Table 43 Disabled Outputs to VREF Resistance
HEADPHONE SWITCH
Pin 43 (GPIO4) can be used as a headphone switch control input to automatically disable the speaker output and enable the headphone output e.g. when a headphone is plugged into a jack socket. In this mode, enabled by setting HPSWEN, pin 43 switches between headphone and speaker outputs (e.g. when pin 43 is connected to a mechanical switch in the headphone socket to detect plug-in). The HPSWPOL bit reverses the polarity of pin 43. Note that the LOUT1, ROUT1, LOUT2 and ROUT2 bits in register 22 must also be set for headphone and speaker output (see Table 44 and Table 45). The GPIO4 pin has an internal pull-up/pull-down which can be enabled by setting register bits GPIO4M[1:0]. For cap-less headphone connections a pull-down should be used if VMID is greater than GPIO4 VIH, otherwise a pull-up should be used. GPIO4 can also be used to generate an interrupt. See GPIO and Interrupt Controller Section. The GPIO4 input has a debounce circuit to remove glitches on the input caused by a jack insert in order to prevent the outputs being powered on and off. This debounce circuit is clocked from a slow clock with period = 221 x input clock. The input clock can be selected to be either mclk or pcmclk using SLWCLK.
HPSWEN 0 0 0 0 1 1 1 1 1 1 1 1
HPSWPOL X X X X 0 0 0 0 1 1 1 1
GPIO4 (pin 43) X X X X 0 0 1 1 1 1 0 0
L/ROUT1 (reg. 22) 0 0 1 1 X X 0 1 X X 0 1
L/ROUT2 (reg. 22) 0 1 0 1 0 1 X X 0 1 X X
Headphone enabled no no yes yes no no no yes no no no yes
Speaker enabled no yes no yes no yes no no no yes no no
Table 44 Headphone Switch Operation
REGISTER ADDRESS R45 (2Dh) Output Control 6
BIT
LABEL HPSWEN 0
DEFAULT
DESCRIPTION Headphone Switch Enable 0 : Headphone switch disabled 1 : Headphone switch enabled Headphone Switch Polarity 0 : GPIO4 high = headphone 1 : GPIO4 high = speaker Timeout and Headphone switch clock source 0 = mclk 1 = pcm clk
5
HPSWPOL
0
R52 (34h) Clock Control
0
SLWCLK
0
Table 45 Headphone Switch
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REGISTER ADDRESS R27 (1Bh) GPIO Control (1) BIT 4:3 LABEL GPIO4M[2:0] DEFAULT 00
Advanced Information
DESCRIPTION Configures GPIO4 pin: 000 = Input only. 001 = unused. 010 = input only with pull-down. 011 = Input only with pull-up. 100 = Drive low. 101 = Drive high. 110 = SDOUT from control interface 111 = INT from interrupt controller
Table 46 GPIO4 Control
THERMAL SHUTDOWN
The speaker and headphone outputs can drive very large currents. To protect the WM8753L from overheating a thermal shutdown circuit is included. If the device temperature reaches approximately 1500C and the thermal shutdown circuit is enabled (TSDEN = 1 ) then the speaker and headphone amplifiers (outputs OUT1L/R, OUT2L/R, OUT3 and OUT4) will be disabled if TSDADEN is set. The thermal shutdown may also be configured to generate an interrupt. See the GPIO and Interrupt Controller section for details. REGISTER ADDRESS R45 (2Dh) Output Control R63 (3Fh) Additional Control 4 BIT LABEL TSDEN 0 DEFAULT DESCRIPTION Thermal Shutdown Enable 1 : thermal shutdown disabled 0 : thermal shutdown enabled Thermal Shutdown Control 0 : Thermal shutdown will not disable speaker and headphone outputs 1 : Thermal shutdown will automatically disable speaker and headphone outputs
6
TSDADEN
0
Table 47 Thermal Shutdown
HEADPHONE OUTPUT
Analogue outputs LOUT1/ROUT1, LOUT2/ROUT2, and OUT3/OUT4, can drive a 16 or 32 headphone load, either through DC blocking capacitors, or DC coupled without any capacitor.
Headphone Output using DC blocking capacitors
DC Coupled Headphone Output (OUT3SW = 00 or OUT4SW=00)
LOUT1/2 ROUT1/2 WM8753L
C1 220uF
LOUT1/2
C2 220uF HPGND = 0V
WM8753L
ROUT1/2 OUT3/OUT4 = VREF
Figure 11 Recommended Headphone Output Configurations When DC blocking capacitors are used, then their capacitance and the load resistance together determine the lower cut-off frequency, fc. Increasing the capacitance lowers fc, improving the bass response. Smaller capacitance values will diminish the bass response. Assuming a 16 load and C1, C2 = 220F: fc = 1 / 2 RLC1 = 1 / (2 x 16 x 220F) = 45 Hz In the DC coupled configuration, the headphone "ground" is connected to the OUT3 or OUT4 pin. OUT3 is enabled by setting OUT3 = 1 and OUT3SW = 00, while OUT4 is enabled by setting OUT4=1 and OUT4SW=00. As the OUT3 pin produces a DC voltage of AVDD/2 (=VREF), there is no DC offset between LOUT1/ROUT1 and OUT3, and therefore no DC blocking capacitors are required. This saves space and material cost in portable applications.
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WM8753L
It is recommended to connect the DC coupled headphone outputs only to headphones, and not to the line input of another device. Although the built-in short circuit protection will prevent any damage to the headphone outputs, such a connection may be noisy, and may not function properly if the other device is grounded.
SPEAKER OUTPUT
LOUT2 and ROUT2 can differentially drive a mono 8 speaker as shown below.
LEFT MIXER
LOUT2
WM8753L
ROUT2INV = 1 -1
LOUT2VOL
VSPKR = L-(-R) = L+R
ROUT2
RIGHT MIXER
ROUT2VOL
Figure 12 Speaker Output Connection The right channel is inverted by setting the ROUT2INV bit, so that the signal across the loudspeaker is the sum of left and right channels. Alternatively it is possible to drive 2 BTL stereo speakers, one between LOUT2 and OUT4, the other between ROUT2 and OUT3, but only to about 250mW/2 due to the limited drive capability of the OUT3/OUT4 outputs.
LINE OUTPUT
The analogue outputs, LOUT1/ROUT1 and LOUT2/ROUT2, can be used as line outputs. Additionally, OUT3 and MONO2 can be used as a stereo line-out by setting OUT3SW=11 (reg. 24) and ensuring the contents of registers 38 and 39 (mono-out mix) are the same as reg. 34 and 35 (left out mix). Recommended external components are shown below.
C1 1uF LOUT1/2 R1 100 Ohm LINE-OUT SOCKET (LEFT) AGND
WM8753L
ROUT1/2 C2 1uF R2 100 Ohm
LINE-OUT SOCKET (RIGHT) AGND
Figure 13 Recommended Circuit for Line Output The DC blocking capacitors and the load resistance together determine the lower cut-off frequency, fc. Assuming a 10 k load and C1, C2 = 1F: fc = 1 / 2 (RL+R1) C1 = 1 / (2 x 10.1k x 1F) = 16 Hz Increasing the capacitance lowers fc, improving the bass response. Smaller values of C1 and C2 will diminish the bass response. The function of R1 and R2 is to protect the line outputs from damage when used improperly.
INTERRUPT CONTROLLER
The WM8753L can generate an interrupt based on seven separate level-sensitive sources. Each source has programmable polarity and can be individually enabled. On detecting an enabled request with the correct polarity, a status latch for that source is set. If any of the status latches are set, the interrupt controller generates an internal INT signal that can be routed to one of the general purpose pins. The value of the status latches can be obtained over the control interface using the read/write mode. Each latch is cleared by disabling the source in question. Once cleared, the source can be reenabled if desired. Figure 14 illustrates the operation of the interrupt controller circuit.
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Advanced Information
HOST
Write R27/R28 to configure GPIO INT pin
WM8753
The interupt controller in the WM8753 is level sensitive, ensuring that interupts are always detected even without a clock. This flowchart illustrates headphone detection, but the same principle applies to the other interrupt sources.
Set HPSWIPOL in register R25
Set HPSWIEN in register R26
WM8753 will interrupt when headphones connected
user connects headphones or headphones already connected
Host enters interrupt mode
INT virtual pin activated
Read interrupt status [SR5] (when multiple source enabled)
SR_IHPDET will be set if interrupt caused by headphones.
Read device status [SR4] (optional)
SR_HPDET will indicate the current status of the headphones. user disconnects headphones or headphones already disconnected
Clear HPSWIEN
INT pin deactivated if no other interrupts
Invert HPSWIPOL
Set HPSWIEN
Will now interrupt when headphones disconnected
Figure 14 Interrupt Control Flowchart
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Advanced Information
WM8753L
REGISTER ADDRESS R25 (19h) Interrupt Polarity
BIT 7
LABEL TSDIPOL
DEFAULT 0
DESCRIPTION Controls polarity of thermal shutdown interrupts. 0 = Interrupt when thermal shutdown active. 1 = Interrupt when thermal shutdown inactive. Controls polarity of Headphone interrupts. 0 = Interrupt when headphone connected. 1 = Interrupt when headphone disconnected. Controls polarity of GPIO5 interrupts. 0 = Interrupt when GPIO5 high. 1 = Interrupt when GPIO5 low. Controls polarity of GPIO4 interrupts. 0 = Interrupt when GPIO4 high 1 = Interrupt when GPIO4 low Controls polarity of GPIO3 interrupts. 0 = Interrupt when GPIO3 high 1 = Interrupt when GPIO3 low Controls polarity of microphone bias detect interrupt 0 = Interrupt when above threshold 1 = Interrupt when below threshold Controls polarity of microphone bias short circuit interrupts. 0 = Interrupt when bias over current 1 = Interrupt when bias normal Controls thermal shutdown interrupt. 1 = Enable interrupt. 0 = Disable interrupt. Controls headphone interrupt. 1 = Enable interrupt. 0 = Disable interrupt. Controls GPIO5 interrupt. 1 = Enable interrupt. 0 = Disable interrupt. Controls GPIO4 interrupt. 1 = Enable interrupt. 0 = Disable interrupt. Controls GPIO3 interrupt. 1 = Enable interrupt. 0 = Disable interrupt. Controls Microphone Bias detect interrupt 1 = Enable interrupt. 0 = Disable interrupt. Controls microphone bias short circuit interrupt (button press). 1 = Enable interrupt. 0 = Disable interrupt. Controls INT signal from controller. 00 = Disabled (no interrupts). 01 = Open drain active low INT signal. 10 = Active high INT signal. 11 = Active low INT signal. Note that physical pin used for INT is controlled via GPIO Control register.
6
HPSWIPOL
0
5
GPIO5IPOL
0
4
GPIO4IPOL
0
3
GPIO3IPOL
0
1
MICDETPOL
0
0
MICSHTPOL
0
R26 (1Ah) Interrupt Mask
7
TSDIEN
0
6
HPSWIEN
0
5
GPIO5IEN
0
4
GPIO4IEN
0
3
GPIO3IEN
0
1
MICDETEN
0
0
MICSHTEN
0
R27 (1Bh) Interrupt Control (1)
8:7
INTCON
00
Table 48 Interrupt Control
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GENERAL PURPOSE INPUT/OUTPUT
The WM8753L has four dual purpose input/output pins.
Advanced Information
* GP1/CLK1: General purpose output 1, or PLL1 clock output. * GP2/CLK2: General purpose output 2, or PLL2 clock output. * GPIO3: General purpose input/output 3 and control interface mode selection input. * GPIO4: General purpose input/output 4, or head phone detection input. * GPIO5: General purpose input/output 5 and control interface chip/address select input.
Pin 44 (MODE/GPIO3) is sampled on powerup to determine the control interface mode (2-wire or 3wire) of the WM8753L. After powerup pin 43 may be used as a GPIO, its use configurable using GPIO3M[2:0]. Pin 45 (CSB/GPIO5) is also sampled on powerup. If 2-wire interface control mode is the value on pin 45 on powerup is used to select the 2-wire address. After powerup, if 2-wire mode is selected, pin 44 may be used as a GPIO, its use configurable using GPIO5M[1:0]. If 3-wire control interface mode is selected pin 44 is always configured as an input and is used as the 3-wire interface latch signal. Pin 43 (GPIO4) is a dedicated GPIO pin with TTL compatible input thresholds and CMOS output thresholds relative to DBVDD, making it ideal for headphone detection. It also features an optional pull-up/pull-down resistor. GPIO4M[2:0] is used to configure the GPIO4 pin. Pins 13 and 14 (GP1/CLK1 and GP2/CLK2) are general purpose outputs and may be configured to either output the PLL clock outputs or may be used as general purpose outputs. They are configured using GP1M[2:0] and GP2M[2:0]. In 3-wire interface mode pin GPIO5/CSB cannot be used as a GPIO as it is used to latch the data. Setting GPIO5M to 01, 10 or 11 will prevent the device from being written to in 3-wire mode. GP2/CLK2 may be configured to output a clock at 256 x the ADC or Hi-Fi DAC sample rate frequency (fs), e.g. if DAC sample rate is set to 8kHz (SR = 00110) output clock will be 256 x 8kHz = 2.048MHz.
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WM8753L
REGISTER ADDRESS R27 (1Bh) GPIO Control (1)
BIT 4:3
LABEL GPIO5M[1:0]
DEFAULT 00
DESCRIPTION Configures GPIO5 pin. (2-wire interface mode only) 00 = Input only. 01 = INT from interrupt controller. 10 = Drive low. 11 = Drive high. Configures GPIO4 pin. 000 = Input only. 001 = unused. 010 = input only with pull-down. 011 = Input only with pull-up. 100 = Drive low. 101 = Drive high. 110 = SDOUT from control interface 111 = INT from interrupt controller Configures GPIO3 pin 000 = Input only. 001 to 011 Reserved. 100 = Drive low. 101 = Drive high. 110 = SDOUT from control interface. 111 = INT from interrupt controller. Configures GP2/CLK2 pin when CLK2EN=0 000 = Drive low. 001 = Drive high. 010 = SDOUT from control interface. 011 = INT from interrupt controller. 100 = ADC clock (=256 x fs) 101 = Hi-Fi DAC clock (=256 x fs) 110 = ADC clock divided by 2 111 = DAC clock divided by 2 Configures GP1/CLK1 pin when CLK1EN=0 000 = Drive low. 001 = Drive high. 010 = SDOUT from control interface. 011 = INT from interrupt controller. 100 to 111 = reserved
2:0
GPIO4M[2:0]
000
R28 (1Ch) GPIO Control (2)
8:6
GPIO3M[2:0]
000
5:3
GP2M[2:0]
000
2:0
GP1M[2:0]
000
Table 49 GPIO Control Note: GPIO5 must not be used in 3-wire interface mode. GPIO5 pin is shared with 3-wire interface CSB. Enabling GPIO5 as an output will prevent 3-wire writes to the WM8753L.
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DIGITAL AUDIO INTERFACES
Advanced Information
The WM8753L has two audio interfaces - a hi-fi audio interface and a voice audio interface. The hi-fi audio interface is used for the input of data to the hi-fi DAC and may also be used to output data from the stereo voice ADC. The voice audio interface is used for the input of data to the voice DAC and for output of data from the voice ADC.
HI-FI AUDIO INTERFACE
The Hi-Fi audio interface has four pins:
* * * *
ADCDAT: ADC data output DACDAT: DAC data input LRC: Data alignment clock BCLK: Bit clock, for synchronisation
The clock signals BCLK, and LRC can be outputs when the WM8753L operates as a master, or inputs when it is a slave (see Master and Salve Mode Operation, below). Four different audio data formats are supported:
* * * *
Left justified Right justified 2 IS DSP mode
All four of these modes are MSB first. They are described in Audio Data Formats, below. Refer to the Electrical Characteristic section for timing information.
VOICE AUDIO INTERFACE
The voice audio interface has four pins:
* * * *
VXDOUT: voice ADC data output VXDIN: voice DAC data input VXFS: data alignment clock or frame sync VXCLK: Bit clock, for synchronisation
The clock signals VXCLK, and VXFS can be outputs when the WM8753L operates as a master, or inputs when it is a slave (see Master and Slave Mode Operation, below). A mixed master/slave mode is also supported where BCLK and VXCLK are outputs from the WM8753L but DACLRC, ADCLRC and VXFS are inputs. The same four audio modes are supported. The interface can also operate in mono mode where only the left or right channel data is transferred. The DATASEL bits can be used to configure which of the ADCs data is output.
MASTER AND SLAVE MODE OPERATION
The WM8753L audio interfaces may be individually configured as either master or slave interfaces. As a master Hi-Fi interface device the WM8753L generates BCLK and LRC and thus controls sequencing of the data transfer on ADCDAT and DACDAT. As a master voice interface device the WM8753L generates VXCLK and VXFS and thus controls sequencing of the data transfer on VXDIN and VXDOUT. In slave modes, the WM8753L responds with data to clocks it receives over the digital audio interfaces. These modes can be selected by writing to the MS and PMS bits. With the interface configured as a Master the LRC and VXFS outputs may be disabled and configured as inputs using LRCOE and VXFSOE for an external frame sync from the controller to be input. In this mode the generated LRC and VXFS must adhere to the timing requirements diagrams detailed in the Signal Timing Requirements section on page 8. Master, slave and mixed modes are illustrated below.
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Advanced Information
WM8753L
Figure 15a Master Mode
Figure 15b Slave Mode
Figure 15c Mixed Mode
AUDIO DATA FORMATS - AUDIO INTERFACE AND VOICE INTERFACE
In Left Justified mode, the MSB is available on the first rising edge of BCLK following an LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles before each LRC transition.
1/fs
LEFT CHANNEL LRC / VXFS BCLK / VXCLK DACDAT / ADCDAT / VXDIN / VXDOUT
RIGHT CHANNEL
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 16 Left Justified Audio Interface (assuming n-bit word length) In Right Justified mode, the LSB is available on the last rising edge of BCLK before a LRC transition. All other bits are transmitted before (MSB first). Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles after each LRC transition.
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1/fs
Advanced Information
LEFT CHANNEL LRC / VXFS BCLK / VXCLK DACDAT / ADCDAT / VXDIN / VXDOUT
RIGHT CHANNEL
1
2
3
n-2 n-1
n
1
2
3
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 17 Right Justified Audio Interface (assuming n-bit word length) In I2S mode, the MSB is available on the second rising edge of BCLK following a LRC transition. The other bits up to the LSB are then transmitted in order. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of one sample and the MSB of the next.
1/fs
LEFT CHANNEL LRC / VXFS BCLK / VXCLK DACDAT / ADCDAT / VXDIN / VXDOUT
1 BCLK 1 2 3 n-2 n-1 n 1 BCLK 1 2 3
RIGHT CHANNEL
n-2 n-1
n
MSB
LSB
MSB
LSB
Figure 18 I2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the left channel MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of BCLK (selectable by LRP) following a rising edge of LRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample.
1/fs 1 BCLK / VXCLK
LRC / VXFS BCLK / VXCLK
LEFT CHANNEL DACDAT / ADCDAT / VXDIN / VXDOUT
1 2 3 n-2 n-1 n 1 2
RIGHT CHANNEL
3 n-2 n-1 n
MSB
Input Word Length (WL)
LSB
Figure 19 DSP Mode Audio Interface (mode A, LRP/PLRP=0)
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Advanced Information
1/fs 1 BCLK / VXCLK
WM8753L
LRC / VXFS BCLK / VXCLK
LEFT CHANNEL DACDAT / ADCDAT / VXDIN / VXDOUT
1 2 3 n-2 n-1 n 1 2
RIGHT CHANNEL
3 n-2 n-1 n
MSB
Input Word Length (WL)
LSB
Figure 20 DSP Mode Audio Interface (mode B, LRP/PLRP=1) The Voice Interface may be configured for Mono mode, where only one channel of data is input or output. In this mode the interface should be configured for DSP mode. A short or long frame sync is supported and the MSB is available on either the 1st (mode B) or 2nd (mode A) rising edge of VXCLK.
1/fs 1 VXCLK
VXFS
VXCLK
VXDIN / VXDOUT
1
2
3
n-2 n-1
n
MSB
Input Word Length (WL)
LSB
Figure 21 Voice Interface Mono Mode (mode A, PLRP=0)
1/fs 1 VXCLK
VXFS
VXCLK
VXDIN / VXDOUT
1
2
3
n-2 n-1
n
MSB
Input Word Length (WL)
LSB
Figure 22 Voice Interface Mono Mode (mode B, PLRP=0)
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AUDIO INTERFACES CONTROL
Advanced Information
The register bits controlling audio format, word length and master / slave mode are summarised below. Each audio interface can be controlled individually. MS selects hi-fi audio interface operation in master or slave mode. In Master mode BCLK, and LRC are outputs. The frequency of LRC is set by the sample rate control bits SR[4:0] and USB. In Slave mode BCLK, and LRC are inputs. PMS selects voice audio interface operation in master or slave mode. In master mode VXCLK and VXFS are outputs. The frequency of VXFS is set by PSR. In slave mode VXCLK and VXFS are inputs. The frequency of BCLK and VXCLK may also be selected by the user under the control of BMODE[2:0] and PBMODE[2:0]. BCLK and VXCLK are divided down versions of master clock and in some settings of BMODE and PBMODE this may result in short BCLK and VXCLK pulses at the end of a frame due to a non-integer ratio of BCLKs or VXCLKS to LRC and VXFS. The WM8753 audio interfaces can be used together in the following modes, under the control of IFMODE[1:0]: 1. 2. 3. 4. Voice Codec operating over Voice interface, with HiFi DAC operating over HiFi interface. Voice Codec operating over HiFi interface, with HiFi DAC disabled. Voice DAC disabled, with HiFi ADC and DAC over HiFi interface. Voice DAC disabled, with HiFi ADC and DAC over HiFi interface, using VXFS as framing signal for ADC data, allowing different sample rates for ADC and DAC.
Additionally each interface can operate in a partial master mode, where the bit clock (BCLK or VXCLK) is generated by the WM8753L, but the framing signal (LRC or VXFS) is derived externally. This mode of operation is selected by selecting Master Mode (by setting MS and/or PMS) and then setting LRCOE and/or VXFSOE to `0' to select LRC and/or VXFS as inputs. In Slave mode (MS and PMS = 0) LRC and VXFS are always inputs. The HiFi DAC audio interface setup is controlled using WL[1:0], FORMAT[1:0] and BCLKINV. The Voice DAC and ADC audio interface setup is controlled using PWL[1:0], PFORMAT[1:0] and VXCLKINV. This allows flexibility in configuring the Voice DAC and ADC separately from the HiFi DAC. Table 50, Table 51 and Table 52 show the configuration for the different interface modes. 1. For Voice Codec and HiFi DAC mode (IFMODE[1:0] = 00) where the Voice DAC and ADC use the Voice interface the wordlength and format for the voice DAC and ADC are set by PWL[1:0] and PFORMAT[1:0]. The wordlength and format for the HiFi DAC using the HiFi interface are set by WL[1:0] and FORMAT[1:0]. For Voice Codec on HiFi interface mode (IFMODE[1:0] = 01) where the Voice DAC and ADC use the HiFi interface the wordlength and format for the voice DAC and ADC are set by PWL[1:0] and PFORMAT[1:0]. For HiFi Codec mode (IFMODE[1:0]=10) when the DAC and ADC both use the HiFi interface, the wordlength and format for the HiFi DAC are set by WL[1:0] and FORMAT[1:0] and the wordlength and format for the ADC are set by PWL[1:0] and PFORMAT[1:0]. In this mode ADC and DAC share the same BCLK and LRC but the format and wordlength for the ADC and DAC can be configured differently. For HiFi Codec mode with ADC and DAC at different sample rates (IFMODE[1:0]=11) when the DAC uses LRC and BCLK and the ADC uses VXFA and BCLK , the wordlength and format for the HiFi DAC are set by WL[1:0] and FORMAT[1:0] and the wordlength and format for the ADC are set by PWL[1:0] and PFORMAT[1:0]. In this mode ADC and DAC share the same BCLK but the format and wordlength for the ADC and DAC can be configured differently.
2.
3.
4.
ADC data is usually output on either ADCDAT or VXDOUT. Under the control of ADCDOP, ADC data can be output on ADCDAT and VXDOUT at the same time. The data on ADCDAT and VXDOUT will be synchronous to either LRC and BCLK or VXFS and VXCLK as set by IFMODE[1:0].
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Advanced Information
WM8753L
Figure 23 Audio Interface Configuration IFMODE[1:0] 00 01 10 11 DAC DATA DACDAT DACDAT DACDAT DACDAT DAC FRAME SYNC LRC LRC LRC LRC DAC BIT CLK BCLK BCLK BCLK BCLK DAC WORDLENGTH WL[1:0] WL[1:0] WL[1:0] WL[1:0] DAC FORMAT FORMAT[1:0] FORMAT[1:0] FORMAT[1:0] FORMAT[1:0]
Table 50 Hi-FI DAC Audio Interface Configuration IFMODE[1:0] 00 01 10 11 ADC DATA VXDOUT ADCDAT ADCDAT ADCDAT ADC FRAME SYNC VXFS LRC LRC VXFS ADC BIT CLK VXCLK BCLK BCLK BCLK ADC WORDLENGTH PWL[1:0] PWL[1:0] PWL[1:0] PWL[1:0] ADC FORMAT PFORMAT[1:0] PFORMAT[1:0] PFORMAT[1:0] PFORMAT[1:0]
Table 51 ADC Audio Interface Configuration IFMODE[1:0] 00 01 10 11 VXDAC DATA VXDAC FRAME SYNC VXDAC BIT CLKVXDAC WORDLENGTH VXDAC FORMAT VXDIN DACDAT VXFS LRC VXCLK BCLK PWL[1:0] PWL[1:0] PFORMAT[1:0] PFORMAT[1:0] -
Table 52 Voice DAC Audio Interface Configuration
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REGISTER ADDRESS R4 (04h) Digital Hi-Fi Audio Interface Format 7 BIT LABEL BCLKINV DEFAULT 0
Advanced Information
DESCRIPTION Hi-Fi DAC BCLK invert bit (for master and slave modes) 0 = BCLK not inverted 1 = BCLK inverted Hi-Fi Interface Master / Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Hi-Fi DAC Left/Right channel swap 1 = swap left and right DAC data in audio interface 0 = output left and right data as normal Hi-Fi DAC right, left and I2S modes - LRC polarity 1 = invert LRC polarity 0 = normal LRC polarity Hi-Fi DAC DSP Mode - mode A/B select 1 = MSB is available on 1st BCLK rising edge after LRC rising edge (mode B) 0 = MSB is available on 2nd BCLK rising edge after LRC rising edge (mode A)
6
MS
0
5
LRSWAP
0
4
LRP
0
3:2
WL[1:0]
10
Hi-Fi DAC Audio Data Word Length 11 = 32 bits (see Note) 10 = 24 bits 01 = 20 bits 00 = 16 bits Hi-Fi DAC Audio Data Format Select 11 = DSP Mode 2 10 = I S Format 01 = Left justified 00 = Right justified
1:0
FORMAT[1:0]
10
Table 53 Audio Data Format Control Note: Right Justified mode does not support 32-bit data.
REGISTER ADDRESS R7 (07h) Digital Audio Interface Control
BIT 8:6
LABEL PBMODE [2:0]
DEFAULT 000
DESCRIPTION Voice Interface Master mode VXCLK rate select 000 : VXCLK = MCLK 001 : VXCLK = MCLK / 2 010 : VXCLK = MCLK / 4 011 : VXCLK = MCLK / 8 100 : VXCLK = MCLK / 16 HiFi Interface Master mode BCLK rate select 000 : BCLK = MCLK 001 : BCLK = MCLK / 2 010 : BCLK = MCLK / 4 011 : BCLK = MCLK / 8 100 : BCLK = MCLK / 16
5:3
BMODE [2:0]
000
Table 54 BCLK and VXCLK Master Mode Rate Select
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Advanced Information
WM8753L
PMS selects Voice audio interface operation in master or slave mode. In Master mode VXCLK and VXFS are outputs. The frequency of FS is set by the sample rate control bits SRMODE and PSR. In Slave mode VXCLK and VXFS are inputs. REGISTER ADDRESS R3 (03h) Digital Voice Audio Interface Format 8 BIT LABEL ADCDOP DEFAULT 0 DESCRIPTION ADC data output to ADCDAT and VXDOUT enable 0 = ADC data output to ADCDAT or VXDOUT as selected by IFMODE[1:0] 1 = ADC data output to ADCDAT and VXDOUT VXCLK invert bit (for master and slave modes) 0 = VXCLK not inverted 1 = VXCLK inverted Voice Interface Master / Slave Mode Control 1 = Enable Master Mode 0 = Enable Slave Mode Mono ADC data only 1 = output left channel ADC data only 0 = output left and right ADC data Vx DAC and ADC right, left and I2S modes VXCLK polarity 1 = invert VXCLK polarity 0 = normal VXCLK polarity Vx DAC and ADC DSP Mode - mode A/B select 1 = MSB is available on 1st VXCLK rising edge after VXFS rising edge (mode B) 0 = MSB is available on 2nd VXCLK rising edge after VXFS rising edge (mode A) 3:2 PWL[1:0] 10 Vx DAC and ADC Audio Data Word Length 11 = 32 bits (see Note) 10 = 24 bits 01 = 20 bits 00 = 16 bits Vx DAC and ADC Audio Data Format Select 11 = DSP Mode 10 = I2S Format 01 = Left justified 00 = Right justified
7
VXCLKINV
0
6
PMS
0
5
MONO
0
4
PLRP
0
1:0
PFORMAT[1: 0]
10
Table 55 Audio Data Format Control Note: Right Justified mode does not support 32-bit data.
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REGISTER ADDRESS R5 (05h) Digital Audio Interface Control BIT 3:2 LABEL IFMODE [1:0] DEFAULT 00
Advanced Information
DESCRIPTION Interface mode 00 = Voice Codec + HiFi DAC. 01 = Voice Codec on HiFi interface. 10 = HiFi over HiFi interface. 11 = HiFi over HiFi interface, using VXFS for ADC frame sync. Configures direction of VXFS pin in master mode 0 = Pin is input 1 = Pin is output Configures direction of LRC pin in master mode 0 = Pin is input 1 = Pin is output
1
VXFSOE
1
0
LRCOE
1
Table 56 Audio Interface Control Control bits VXCLKTRI, BCLKTRI, VXDTRI and ADCDTRI configure the Hi-Fi and Voice interface pins BCLK, VXCLK, ADCDAT and VXDOUT as inputs or tristate. This allows the I2S and PCM interfaces to be connected to an interface bus and all outputs onto the bus tristated or switched to inputs. The default state for all audio interface PMS is input or tristate. REGISTER ADDRESS R5 (05h) Digital Audio Interface Control 7 BIT LABEL VXCLKTRI DEFAULT 0 DESCRIPTION VXCLK tristate 0 = VXCLK pin configured as input or output as set by PMS 1 = VXCLK pin tristated and used as input BCLK tristate 0 = BCLK pin configured as input or output as set by MS 1 = BCLK pin tristated and used as input VXDOUT tristate 0 = VXDOUT pin enabled as output 1 = VXDOUT pin tristated ADCDAT tristate 0 = ADCDAT pin enabled as output 1 = ADCDAT pin tristated
6
BCLKTRI
0
5
VXDTRI
1
4
ADCDTRI
1
Table 57 PCM and Hi-Fi Interface Tristate
CONTROL INTERFACE
SELECTION OF CONTROL MODE AND 2-WIRE MODE ADDRESS
The control interface can operate as either a 3-wire or 2-wire MPU interface. The MODE/GPIO3 pin is sampled at power-up, latched and used to select the interface format. After power-up MODE/GPIO3 is available for general purpose use. The CSB/GPIO5 pin is also sampled and latched on power-up and, if 2-wire mode is selected, the latched value selects the 2-wire mode address. For 3-wire mode CSB/GPIO5 is always an input. After power-up in 2-wire mode CSB/GPIO5 is available for general purpose use. See MODE/GPIO3 and CSB/GPIO5 LATCH on Power-up Timing Information on page 9. The WM8753L is controlled by writing to registers through a serial control interface. A control word consists of 16 bits. The first 7 bits (B15 to B9) are address bits that select which control register is accessed. The remaining 9 bits (B8 to B0) are register bits, corresponding to the 9 bits in each control register.
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Advanced Information MODE/GPIO3 Low High INTERFACE FORMAT 2 wire 3 wire
WM8753L
Table 58 Control Interface Mode Selection
3-WIRE SERIAL CONTROL MODE
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDIN pin. A rising edge on GPIO5/CSB latches in a complete control word consisting of the last 16 bits. In 3-wire mode readback is also available to allow read of a device ID register or interrupt status registers. Readback is enabled by setting READEN. The address of the register to be read back is selected by setting READSEL[2:0]. The readback data can be output on ADCDAT by setting RDDAT or on GPI/CLK1, GP2/CLK2, GPIO3 or GPIO4 by configuring the GPIO pins using control bits GP1M[1:0], GP2M[1:0], GP3M[2:0] and GP4M[2:0]. The SDOUT virtual pin will be tri-state when the CSB pin is high, allowing data from multiple sources to be connected to the same controller.
READEN=0
latch
GPIO5/CSB SCLK SDIN
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
control register address
control register data
READEN=1
SDOUT tri-stated when CSB=1 latch
GPIO5/CSB SCLK SDIN SDOUT
B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
S7
S6
S5
S4
S3
S2
S1
S0
S7
S6
S5
S4
S3
S2
S1
S0
status word
status word (duplicated)
Figure 24 3-Wire Serial Control Interface
2-WIRE SERIAL CONTROL MODE
The WM8753L supports software control via a 2-wire serial bus. Many devices can be controlled by the same bus, and each device has a unique 7-bit device address (this is not the same as the 7-bit address of each register in the WM8753L). The WM8753L operates as a slave device only. The controller indicates the start of data transfer with a high to low transition on SDIN while SCLK remains high. This indicates that a device address and data will follow. All devices on the 2-wire bus respond to the start condition and shift in the next eight bits on SDIN (7-bit address + Read/Write bit, MSB first). If the device address received matches the address of the WM8753L, then the WM8753L responds by pulling SDIN low on the next clock pulse (ACK). If the address is not recognised or the R/W bit is `1' when operating in write only mode, the WM8753L returns to the idle condition and wait for a new start condition and valid address. During a write, once the WM8753L has acknowledged a correct address, the controller sends the first byte of control data (B15 to B8, i.e. the WM8753L register address plus the first bit of register data). The WM8753L then acknowledges the first data byte by pulling SDIN low for one clock pulse. The controller then sends the second byte of control data (B7 to B0, i.e. the remaining 8 bits of register data), and the WM8753L acknowledges again by pulling SDIN low. Transfers are complete when there is a low to high transition on SDIN while SCLK is high. After a complete sequence the WM8753L returns to the idle state and waits for another start condition. If a start or stop condition is detected out of sequence at any point during data transfer (i.e. SDIN changes while SCLK is high), the device jumps to the idle condition.
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WM8753L
Advanced Information
Figur e 25 2-Wire Serial Control Interface The WM8753L has two possible device addresses, which can be selected using the GPIO5/CSB pin. The pin is sampled at power-up and selects the device address. After power-up the pin is available for general purpose use in 2-wire interface mode. GPIO5/CSB STATE Low High Table 59 2-Wire MPU Interface DEVICE ADDRESS 0011010 0011011
READ/WRITE OPERATION
The control interface of the WM8753L is a write only interface. However setting register bit READEN in 3-wire mode will allow a status word to be read from the device. A status word consists of 8 bits. Different status words are supported by the device, and are selected by changing the READSEL register bits. The supported words are listed in Table 60. In 3-wire mode an additional pin is required for serial data output from the device. This data can be routed to the ADCDAT, GP1, GP2, GPIO3 or GPIO4 pins. The pin will be tri-state when the CSB pin is high, allowing data from multiple sources to be connected to the same controller. In 3-wire mode, reads and write occur simultaneously (i.e. data is clocked in and out at the same time). Usually a read can be paired with a write, but if this is not possible it is recommended that reads be paired with a dummy write to register R0, which is unused. REGISTER ADDRESS R24 (18h) Read Control 4 BIT LABEL RDDAT DEFAULT 0 DESCRIPTION Selects ADCDAT as SDOUT for 3-wire readback 0 = ADCDAT not selected for readback 1 = ADCDAT selected for readback Read register select See table Table 61 below Control interface read enable 0 = Control interface is write only 1 = Control interface supports read and write.
3:1 0
READSEL READEN
000 0
Table 60 Control Interface Control
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Advanced Information
WM8753L
BIT 7:0 7:0 7:0 7:0 7 LABEL SR_IDHI SR_IDLO SR_REV SR_CAP SR_TSD DEFAULT 87h 53h 01h 00h 0 Device revision Device capabilities. Thermal shutdown state. 1 = Thermal shutdown detected. 0 = Normal operation. Headphone or speaker detect state (see HPSWEN and HPSWPOL). 1 = Headphones connected 0 = Headphones disconnected GPIO5 state. 0 = GPIO5 pin low 1 = GPIO5 pin high GPIO4 state. 0 = GPIO4 pin low 1 = GPIO4 pin high GPIO3 state. 0 = GPIO3 pin low 1 = GPIO3 pin high Microphone bias threshold state 1 = above threshold 0 = below threshold Microphone bias short circuit state. 1 = Bias short circuit detected 0 = Bias current OK Thermal shutdown interrupt 1 = Interrupt. 0 = No interrupt. Headphone detection interrupt. 1 = Interrupt. 0 = No interrupt. GPIO5 interrupt. 1 = Interrupt. 0 = No interrupt. GPIO4 interrupt. 1 = Interrupt. 0 = No interrupt. GPIO3 interrupt. 1 = Interrupt. 0 = No interrupt. Microphone bias threshold interrupt Microphone bias short circuit interrupt DESCRIPTION Indicates that device is an 8753L
READSEL STATUS REGISTER [3:1] VALUE ADDRESS 000 001 010 011 100 SR0 (0h) Device ID high SR1 (1h) Device ID low SR2 (2h) Device revision SR3 (3h) Device capabilities SR4 (4h) Device status
6
SR_HPDET
0
5
SR_GPIO5
0
4
SR_GPIO4
0
3
SR_GPIO3
0
1
SR_IMICDET
0
0
SR_IMICSHT
0
101
SR5 (5h) Interrupt status
7
SR_ITSD
0
6
SR_IHPDET
0
5
SR_IGPIO5
0
4
SR_IGPIO4
0
3
SR_IGPIO3
0
1 0 Table 61 Status Words
SR_IMICDET SR_IMICSHT
0 0
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MASTER CLOCK AND PHASE LOCKED LOOP
Advanced Information
The WM8753L has two on-chip phase-locked loop (PLL) circuits that can be used to: * Generate master clocks for the WM8753L audio functions from another external clock, e.g. in telecoms applications. Generate a clock for another part of the system from an existing audio master clock.
*
The user must also select the clock for the HiFi DAC, ADC and Voice DAC. The ADC and Voice DAC are always clocked from the same clock source. The HiFi DAC may be clocked from the same or different clock source to the ADC and Voice DAC. For HiFi Codec operation, when the ADC is selected for high quality record, the ADC and DAC must be clocked from the same clock source. The PLL and clock select circuit is shown below.
Figure 26 PLL and Clock Select Circuit REGISTER ADDRESS R52 (34h) Clock Control BIT 8:6 LABEL PCMDIV[2:0] DEFAULT 000 DESCRIPTION Control PCM clock divider 000 = divide by 1 (disable) 001 = Unused 010 = Divide by 3 011 = Divide by 5.5 100 = Divide by 2 101 = Divide by 4 110 = Divide by 6 111 = Divide by 8 Select internal master clock for HiFi Codec 0: from MCLK pin 1: from PLL1 (ensure PLL1EN=1) Select internal master clock for Voice Codec 0: from PCMCLK pin 1: from PLL2 (ensure PLL2EN=1) Select clock for Voice Codec 0: PCMCLK or PLL2 clock 1: same as HiFi DAC (MCLK or PLL1 clock) GP1CLK1 select 0 = GP1 output 1 = CLK1 output GP2/CLK2 select 0 = GP2 output 1 = CLK2 output AI Rev 3.1 June 2004 65
4
MCLKSEL
0
3
PCMCLKSEL
0
2
CLKEQ
1
1
GP1CLK1SEL
0
0
GP2CLK2SEL
0
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Advanced Information R53 (35h) PLL1 Control (1) 5 CLK1SEL 0 CLKOUT1 select 0 : from MCLK pin 1 : from PLL1
WM8753L
4
CLK1DIV2
0
CLKOUT1 Divide by 2 0 : Divide by 2 disabled 1 : Divide by 2 enabled MCLK Divide by 2 0 : Divide by 2 disabled 1 : Divide by 2 enabled PLL1 Output Divide by 2 0 : Divide disabled 1 : Divide enabled PLL1 reset 0 : PLL reset 1 : PLL active PLL 1 Enable 0 : Disabled 1 : Enabled CLKOUT2 select 0 : from MCLK pin 1 : from PLL2 CLKOUT1 Divide by 2 0 : Divide by 2 disabled 1 : Divide by 2 enabled MCLK Divide by 2 0 : Divide by 2 disabled 1 : Divide by 2 enabled PLL2 Output Divide by 2 0 : Divide disabled 1 : Divide enabled PLL2 reset 0 : PLL reset 1 : PLL active PLL2 Enable 0 : Disabled 1 : Enabled
3
MCLK1DIV2
0
2
PLL1DIV2
0
1
PLL1RB
1
0
PLL1EN
0
R57 (39h) PLL2 Control (1)
5
CLK2SEL
0
4
CLK2DIV2
0
3
MCLK2DIV2
0
2
PLL2DIV2
0
1
PLL2RB
1
0
PLL2EN
0
Table 62 PLL and Clocking Control The PLL frequency ratio R = f2/f1 (see Figure 26 ) can be set using K and N: N = int R K = int (222 (R-N))
Example: mclk=12MHz, required clock = 12.288MHz. R should be chosen to ensure 5 < N < 13. There is a divide by 4 and a selectable divide by 2 after the PLL which should be set to meet this requirement. Enabling the divide by 2 sets the required f2 = 8 x 12.288MHz = 98.304MHz. R = 98.304 / 12 = 8.192 N = int R = 8 k = int ( 2 x (8.192 - 8)) = 805306 = C49BAh
22
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REGISTER ADDRESS R54 (36h) PLL1 Control (2) BIT 8:5 LABEL PLL1N DEFAULT 1000
Advanced Information
DESCRIPTION Integer (N) part of PLL1 input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL1 input/output frequency ratio (treat as one 22-digit binary number).
3:0 R55 (37h) PLL1 Control (3) R56 (38h) PLL1 Control (4) 8:0 8:0
PLL1K [21:18] PLL1K [17:9] PLL1K [8:0]
0011 024h 1Bah
Table 63 PLL1 Frequency Ratio Control
REGISTER ADDRESS R58 (3Ah) PLL2 Control (2)
BIT 8:5
LABEL PLL2N
DEFAULT 1000
DESCRIPTION Integer (N) part of PLL2 input/output frequency ratio. Use values greater than 5 and less than 13. Fractional (K) part of PLL2 input/output frequency ratio (treat as one 22-digit binary number)
3:0 R59 (3Bh) PLL2 Control (2) R60 (3Ch) PLL2 Control (3) 8:0 8:0
PLL2K [21:18] PLL2K [17:9] PLL2K [8:0]
0011 024h 1Bah
Table 64 PLL2 Frequency Ratio Control The PLL performs best when f2 is around 90MHz. Its stability peaks at N=8. Some example settings are shown below. MCLK (MHz) (F1) 11.91 11.91 12 12 13 13 14.4 14.4 19.2 19.2 19.68 19.68 19.8 19.8 24 24 26 26 27 27 DESIRED OUTPUT (MHz) 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 11.2896 12.288 F2 (MHz) 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 90.3168 98.304 MCLK DIV2 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 PLL OUT DIV2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CLK OUT DIV2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R N (Hex) 7 8 7 8 6 7 6 6 9 A 9 9 9 9 7 8 6 7 6 7 K (Hex) 25545F 103FF8 21B08A C49BA 3CA2F5 23F54A 116873 34E81B 1A1CAC F5C29 B6D25 3F6028 7DDBE 3B8028 21B08A C49BA 3CA2F5 23F54A 2C2B25 1208A6
7.5833 8.2539 7.5264 8.192 6.9474 7.5618 6.272 6.8267 9.408 10.24 9.1785 9.9902 9.1229 9.9297 7.5264 8.192 6.9474 7.5618 6.6901 7.2818
Table 65 PLL Frequency Examples
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Advanced Information
WM8753L
The WM8753L has two modes of operation for the HiFi DAC, ADC and voice DAC sample rates, selectable using control bit SRMODE: HiFi Codec Mode: SRMODE=0. HiFi DAC and stereo ADC used for high quality playback and record. The Voice DAC is unused. Sample rate control is via control bits SR[4:0] and USB. HiFi DAC + Voice Codec Mode: SRMODE=1. HiFi DAC is used for high quality playback; Stereo (or mono) ADC and voice DAC are used for voice record and playback. HiFi DAC Sample rate is controlled by SR[4:0] and USB. Voice Codec sample rate is controlled by PSR. In either mode of operation the ADCs and DACs may be powered off if not required to allow e.g. HiFi DAC playback only, with ADCs disabled. The HiFi DAC sample rate is always controlled by SR[4:0] and USB.
AUDIO SAMPLE RATES
HIFI CODEC MODE
In this mode the Voice DAC is unused and the stereo ADC is used for HiFi record.The WM8753L may be configured to run from a clock generated by the on-chip PLL or may be driven from an external clock connected to the MCLK pin. The WM8753L supports a wide range of master clock frequencies on the MCLK pin, and can generate many commonly used audio sample rates directly from the master clock. In HiFi Codec Mode the ADC and DAC do not need to run at the same sample rate; several different combinations are possible. There are two clocking modes:
* *
`Normal' mode supports master clocks of 128fs, 192fs, 256fs, 384fs, and their multiples (Note: fs refers to the ADC or DAC sample rate, whichever is faster) USB mode supports 12MHz or 24MHz master clocks. This mode is intended for use in systems with a USB interface, and eliminates the need for the internal PLL to generate the clock frequency for the audio codec. REGISTER ADDRESS BIT 8 LABEL SRMODE 0 DEFAULT DESCRIPTION ADC Sample rate mode 0 - ADC sample rate selected by SR[4:0] and USB 1 - ADC sample rate selected by PSR Sample Rate Control Clocking Mode Select 1 = USB Mode 0 = `Normal' Mode
R6 (06h) Sample Rate Control (1)
[5:1] 0
SR [4:0] USB
00000 0
Table 66 Clocking and Sample Rate Control The clocking of the WM8753L Hi-Fi Codec is controlled using the MCLK1DIV2, USB, and SR control bits. SR allows the user to change the ADC and DAC sample rates without changing the master clock frequency. Setting the MCLK1DIV2 bit divides MCLK by two internally. The USB bit selects between `Normal' and USB mode. Each value of SR[4:0] selects one combination of MCLK division ratios and hence one combination of sample rates (see next page). Since all sample rates are generated by dividing MCLK, their accuracy depends on the accuracy of MCLK. If MCLK changes, the sample rates change proportionately. Note that some sample rates (e.g. 44.1kHz in USB mode) are approximated, i.e. they differ from their target value by a very small amount. This is not audible, as the maximum deviation is only 0.27% (8.0214kHz instead of 8kHz in USB mode). By comparison, a half-tone step corresponds to a 5.9% change in pitch.
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MCLK CLKDIV2=0 12.288MHz MCLK CLKDIV2=1 ADC SAMPLE RATE DAC SAMPLE RATE USB
Advanced Information
SR [4:0]
FILTER TYPE 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 3 1 1 1 1 1 1 1 1 3 1 1 1 1 1 1 3 0 0 1 1 1 0 0 1 0 0 1 1 0 0 3 2
`Normal' Clock Mode (`*' indicates backward compatibility with WM8731) 8 kHz (MCLK/1536) 8 kHz (MCLK/1536) 24.576MHz 8 kHz (MCLK/1536) 48 kHz (MCLK/256) 12 kHz (MCLK/1024) 12 kHz (MCLK/1024) 16 kHz (MCLK/768) 16 kHz (MCLK/768) 24 kHz (MCLK/512) 24 kHz (MCLK/512) 32 kHz (MCLK/384) 32 kHz (MCLK/384) 48 kHz (MCLK/256) 8 kHz (MCLK/1536) 48 kHz (MCLK/256) 48 kHz (MCLK/256) 96 kHz (MCLK/128) 96 kHz (MCLK/128) 8.0182 kHz (MCLK/1408) 8.0182 kHz (MCLK/1408) 11.2896MHz 22.5792MHz 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/256) 11.025 kHz (MCLK/1024) 11.025 kHz (MCLK/1024) 22.05 kHz (MCLK/512) 22.05 kHz (MCLK/512) 44.1 kHz (MCLK/256) 8.0182 kHz (MCLK/1408) 44.1 kHz (MCLK/256) 44.1 kHz (MCLK/256) 88.2 kHz (MCLK/128) 88.2 kHz (MCLK/128) 8 kHz (MCLK/2304) 8 kHz (MCLK/2304) 18.432MHz 36.864MHz 8 kHz (MCLK/2304) 48 kHz (MCLK/384) 12 kHz (MCLK/1536) 12 kHz (MCLK/1536) 16kHz (MCLK/1152) 16 kHz (MCLK/1152) 24kHz (MCLK/768) 24 kHz (MCLK/768) 32 kHz (MCLK/576) 32 kHz (MCLK/576) 48 kHz (MCLK/384) 48 kHz (MCLK/384) 48 kHz (MCLK/384) 8 kHz (MCLK/2304) 96 kHz (MCLK/192) 96 kHz (MCLK/192) 8.0182 kHz (MCLK/2112) 8.0182 kHz (MCLK/2112) 16.9344MHz 33.8688MHz 8.0182 kHz (MCLK/2112) 44.1 kHz (MCLK/384) 11.025 kHz (MCLK/1536) 11.025 kHz (MCLK/1536) 22.05 kHz (MCLK/768) 22.05 kHz (MCLK/768) 44.1 kHz (MCLK/384) 8.0182 kHz (MCLK/2112) 44.1 kHz (MCLK/384) 44.1 kHz (MCLK/384) 88.2 kHz (MCLK/192) 88.2 kHz (MCLK/192) USB Mode (`*' indicates backward compatibility with WM8731) 8 kHz (MCLK/1500) 8 kHz (MCLK/1500) 12.000MHz 24.000MHz 8 kHz (MCLK/1500) 48 kHz (MCLK/250) 8.0214 kHz (MCLK/1496) 8.0214kHz (MCLK/1496) 8.0214 kHz (MCLK/1496) 44.118 kHz (MCLK/272) 11.0259 kHz (MCLK/1088) 11.0259kHz (MCLK/1088) 12 kHz (MCLK/1000) 12 kHz (MCLK/1000) 16kHz (MCLK/750) 16kHz (MCLK/750) 22.0588kHz (MCLK/544) 22.0588kHz (MCLK/544) 24kHz (MCLK/500) 24kHz (MCLK/500) 32 kHz (MCLK/375) 32 kHz (MCLK/375) 44.118 kHz (MCLK/272) 8.0214kHz (MCLK/1496) 44.118 kHz (MCLK/272) 44.118 kHz (MCLK/272) 48 kHz (MCLK/250) 8 kHz (MCLK/1500) 48 kHz (MCLK/250) 48 kHz (MCLK/250) 88.235kHz (MCLK/136) 88.235kHz (MCLK/136) 96 kHz (MCLK/125) 96 kHz (MCLK/125) Table 67 Master Clock and Sample Rates
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
00110 * 00100 * 01000 01010 11100 01100 * 00010 * 00000 * 01110 * 10110 * 10100 * 11000 11010 10010 * 10000 * 11110 * 00111 * 00101 * 01001 01011 11101 01101 * 00001 * 00011 * 01111 * 10111 * 10101 * 11001 11011 10011 * 10001 * 11111 * 00110 * 00100 * 10111 * 10101 * 11001 01000 01010 11011 11100 01100 * 10011 * 10001 * 00010 * 00000 * 11111 * 01110 *
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Advanced Information
WM8753L
HIFI DAC + VOICE CODEC MODE
In this mode the stereo ADC and voice DAC are used for voice record and playback and the HiFi DAC is used for high quality playback. The HiFi DAC may be powered off for voice codec only operation. In this mode the sample rate for the HiFi DAC is controlled using SR[4:0] and USB, as detailed in the HIFI Codec Mode section above. The Voice DAC and ADC sample rate is controlled by PSR. In this mode the Voice DAC and ADC sample rate is derived from the master clock selected for the voice DAC and ADC (see Figure 26). The Voice codec and HiFi DAC may operate at different sample rates from the same or separate master clocks. e.g. for HiFI DAC operation at fs=48kHz and voice codec operation at fs=8kHz with mclk = 12.288MHz. PCMDIV (reg52) should be set to divide mclk by 6 to provide a 2.048Mhz (= 256 x 8kHz) clock for the voice DAC and ADC. REGISTER ADDRESS R6 (06h) Sample Rate Control 8 BIT LABEL SRMODE 0 DEFAULT DESCRIPTION ADC Sample rate mode 0 - ADC sample rate selected by SR[4:0] and USB 1 - ADC sample rate selected by PSR[1:0] Voice Codec Sample Rate Control 0 - 256fs mode 1 - 384fs mode
7
PSR
0
Table 68 Clocking and Sample Rate Control The clocking of the WM8753L voice codec is controlled using the PSR control bits. If MCLK changes, the sample rates change proportionately.
POWER SUPPLIES
The WM8753L can use up to four separate power supplies: AVDD and AGND: Analogue supply, powers all analogue functions except the headphone drivers. AVDD can range from 1.8V to 3.6V and has the most significant impact on overall power consumption (except for power consumed in the headphone). A large AVDD slightly improves audio quality. HPVDD, SPKRVDD and HP/SPKRGND: Headphone and Speaker supplies, power the headphone and speaker drivers. HPVDD and SPKRVDD can range from 1.8V to 3.6V. HPVDD and SPKRVDD are normally tied to AVDD, but it requires separate layout and decoupling capacitors to curb harmonic distortion. With a larger HPVDD and SPKRVDD, louder headphone and speaker outputs can be achieved with lower distortion. If HPVDD and /or SPKRVDD are lower than AVDD, the output signal may be clipped. PLLVDD and PLLGND. PLL supplies, power the two on-chip PLLs. PLLVDD can range from 1.8V to 3.6V. DCVDD: Digital core supply, powers all digital functions except the audio and control interfaces. DCVDD can range from 1.42V to 3.6V, and has no effect on audio quality. The return path for DCVDD is DGND, which is shared with DBVDD. DBVDD: Digital buffer supply, powers the audio and control interface buffers. This makes it possible to run the digital core at very low voltages, saving power, while interfacing to other digital devices using a higher voltage. DBVDD draws much less power than DCVDD, and has no effect on audio quality. DBVDD can range from 1.8V to 3.6V. The return path for DBVDD is DGND, which is shared with DCVDD.

It is possible to use the same supply voltage on all four. However, digital and analogue supplies should be routed and decoupled separately to keep digital switching noise out of the analogue signal paths.
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POWER MANAGEMENT
Advanced Information
The WM8753L has three control registers that allow users to select which functions are active. For minimum power consumption, unused functions should be disabled. To avoid any pop or click noise, it is important to enable or disable functions in the correct order (see Applications Information). VMIDSEL is the enable for the Vmid reference, which defaults to disabled and can be enabled as a 50k potential divider or, for low power maintenance of Vref when all other blocks are disabled, as a 500k potential divider. REGISTER ADDRESS R20 (14h) Power Management (1) BIT 8:7 LABEL VMIDSEL DEFAULT 00 DESCRIPTION Vmid divider enable and select 00 - Vmid disabled (for OFF mode) 01 - 50k divider enabled (for playback/record) 10 - 500k divider enabled (for low-power standby) 11 - 5k divider enabled (for fast start-up) VREF enable (necessary for functions) MIC Bias enable Voice DAC enable DAC Left enable DAC Right enable Disables MCLK into digital Mic1 preamp enable Mic2 preamp enable ALC mixer enable ADC left PGA enable ADC right PGA enable Left ADC enable Right ADCR enable RX mixer enable Line mixer enable LOUT1 enable ROUT1 enable LOUT2 enable ROUT2 enable OUT3 enable OUT4 enable MONO1 enable MONO2 enable Record Mixer Enable Mono mixer enable Right mixer enable Left mixer enable all other
6 5 4 3 2 0 R21 (15h) Power Management (2) 8 7 6 5 4 3 2 1 0 R22 (16h) Power Management (3) 8 7 6 5 4 3 2 1 R23 (17h) Power Management (4) 3 2 1 0
VREF MICB VDAC DACL DACR DIGENB MICAMP1EN MICAMP2EN ALCMIX PGAL PGAR ADCL ADCR RXMIX LINEMIX LOUT1 ROUT1 LOUT2 ROUT2 OUT3 OUT4 MONO1 MONO2 RECMIX MONOMIX RIGHTMIX LEFTMIX
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Note: All control bits are 0=OFF, 1=ON Table 69 Power Management
SAVING POWER AT LOW SUPPLY VOLTAGES
The analogue supplies to the WM8753L can run from 1.8V to 3.6V. By default, all analogue circuitry on the device is optimized to run at 3.3V. This set-up is also good for all other supply voltages down to 1.8V. However, at lower voltages, it is possible to save power by reducing the internal bias currents used in the analogue circuitry. This is controlled as shown below.
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Advanced Information
WM8753L
REGISTER ADDRESS R18 (12h) Additional Control BIT 7:6 LABEL VSEL [1:0] DEFAULT 11 DESCRIPTION Analogue Bias optimization 00: Lowest bias current, optimized for AVDD=1.8V 01: Low bias current, optimized for AVDD=2.5V 1X: Default bias current, optimized for AVDD=3.3V
SAVING POWER BY REDUCING OVERSAMPLING RATE
The default mode of operation of the ADC and DAC digital filters is in 64x oversampling mode. Under the control of ADCOSR and DACOSR the oversampling rate may be doubled. 64x oversampling results in a slight decrease in noise performance compared to 128x but lowers the power consumption of the device. ADC 64x mode is not available in USB mode (USB = 1). In USB mode ADCOSR must be set to `0'. REGISTER ADDRESS R7 (07h) Sample Rate Control (2) 2 BIT LABEL VXDACOSR 1 DEFAULT DESCRIPTION Voice DAC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR) ADC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR) DAC oversample rate select 1 = 64x (lowest power) 0 = 128x (best SNR)
1
ADCOSR
1
0
DACOSR
1
Table 70 ADC and DAC Oversampling Rate Selection
SAVING POWER BY REDUCING BIAS CURRENTS
There are various biasing options within the WM8753L for increasing or reducing the bias current that is used by sections of the chip. The control of these is via the register bits MBIASBOOST, VDACBIASX0P5, MICBIASBST, BUFBIAS, IPBIASX0P5, ADCBIAS, OPBIASX0P5 and DMBIASX0P5 as shown in Figure 27. The performance of the chip may vary when the bias currents are changed from the default.
MBIASBOOST 0=x1 1=x1.5
masterbias
clkdet
BUFBIAS[1:0] 00=x1 2 01=x0.25 10=x0.5 11=x1.5
s/h buffer s/h buffer
ADCBIAS[1:0] 00=x1 2 01=x0.25 10=x0.5 11=x1.5
adc adc
MICBIASBST[1:0] 2 00=x1 01=x2 micpreamp 10=x3 11=x4 micpreamp IPBIASX0P5 0=x1 1=x0.5 DMBIASX0P5 0=x1 1=x0.5
clkdet
VDACBIASX0P5 0=x1 1=x0.5 local biasgen
local biasgen
OPBIASX0P5 0=x1 1=x0.5
local biasgen
adc pga & zc
adc pga & zc
line mix
rx mix voice dac hp pga & zc hp pga & zc mono 2
dac adc mixinv adc mixinv mic detect alc mix
dac
rec mix
out3
out4
mixl
mixr
mixm
dacinv
dacinv
dacinv
spkr pga & zc
spkr pga & zc
mono pga & zc
Figure 27 Bias Current Control
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REGISTER ADDRESS R61 (3Dh) Bias control BIT 8 LABEL VDACBIASX0P5 DEFAULT 0
Advanced Information
DESCRIPTION Voice DAC bias current reduce: 0 = 1x bias 1 = 0.5x bias (reduced power) Master bias current boost 0 = 1x bias 1 = 1.5x bias (increased power) Microphone preamplifier current boost: 00 = 1x bias 01 = 2x bias 10 = 3x bias 11 = 4x bias ADC sample and hold buffer bias control: 00 = 1x bias 01 = 0.25x bias (lowest power) 10 = 0.5x bias (reduced power) 11 = 1.5x bias (increased power) ADC volume control (PGA) ADCINV bias reduce: 0 = 1x bias 1 = 0.5x bias (reduced power) ADC bias current reduce: 00 = 1x bias 01 = 0.25x bias (lowest power) 10 = 0.5x bias (reduced power) 11 = 1.5x bias (increased power) and
7
MBIASBOOST
0
[6:5]
MICBIASBST [1:0]
00
[4:3]
BUFBIAS[1:0]
00
2
IPBIASX0P5
0
[1:0]
ADCBIAS[1:0]
00
Table 71 Bias Control Bits
REGISTER ADDRESS R63 (3Fh) Additional control
BIT 1
LABEL OPBIASX0P5
DEFAULT 0
DESCRIPTION Analogue Output bias current control: 0 = 1x bias 1 = 0.5x bias (reduced power) DAC and Mixer bias current control: 0 = 1x bias 1 = 0.5x bias (reduced power)
0
DMBIAS0P5
0
Table 72 Additional Control Register - Bias Control Bits
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Advanced Information
WM8753L
REGISTER MAP
ADDRESS REGISTER (Bit 15:9) R1 (01h) R2 (02h) R3 (03h) 0000001 0000010 0000011 Interface Hi-Fi Audio R4 (04h) R5 (05h) R6 (06h) 0000100 Interface 0000101 0000110 (1) Sample Rate Ctrl R7 (07h) R8 (08h) R9 (09h) R10 (0Ah) R11 (0Bh) R12 (0Ch) R13 (0Dh) R14 (0Eh) R15 (0Fh) R16 (10h) R17 (11h) R18 (12h) R19 (13h) R20 (14h) R21 (15h) R22 (16h) R23 (17h) R24 (18h) R25 (19h) 0000111 (2) 0001000 0001001 0001010 0001011 0001100 0001101 0001110 0001111 0010000 0010001 0010010 0010011 0010100 0010101 0010110 0010111 0011000 0011001 Left DAC volume Right DAC volume Bass control Treble control ALC1 ALC2 ALC3 Noise Gate Left ADC volume Right ADC volume Additional control 3D Control Pwr Mgmt (1) Pwr Mgmt (2) Pwr Mgmt (3) Pwr Mgmt (4) ID register Interupt Polarity LDVU RDVU 0 0 BB 0 TC BC[2:0] 0 MAXGAIN[2:0] ALCSR[3:0] DCY[3:0] NGTH[4:0] LADCVOL[7:0] RADCVOL[7:0] VSEL[1:0] MODE3D 3DUC VREF ALCMIX LOUT2 0 0 HPSW 0 TSDIPOL IPOL R26 (1Ah) R27 (1Bh) R28 (1Ch) R31 (1Fh) R32 (20h) R33 (21h) R34 (22h) R35 (23h) R36 (24h) R37 (25h) R38 (26h) R39 (27h) R40 (28h) R41 (29h) R42 (2Ah) R43 (2Bh) R44 (2Ch) R45 (2Dh) 0011010 0011011 0011100 0011111 0100000 0100001 0100010 0100011 0100100 0100101 0100110 0100111 0101000 0101001 0101010 0101011 0101100 0101101 Interupt Enable GPIO Control (1) GPIO Control (2) Reset Record Mix (1) Record Mix (2) Left out Mix (1) Left out Mix (2) Right out Mix (1) Right out Mix (2) Mono out Mix (1) Mono out Mix (2) LOUT1 volume ROUT1 volume LOUT2 volume ROUT2 volume MONOOUT volume Output Control 0 0 LD2LO VXD2LO RD2RO VXD2RO LD2MO RD2MO LO1VU RO1VU LO2VU RO2VU 0 0 TSDIEN HPSWIEN IEN INTCON[1:0] GPIO3M[2:0] 0 0 IEN IEN GPIO5M[1:0] GP2M[2:0] IPOL GPIO5 IPOL GPIO4 IPOL GPIO3 0 IEN GPIO4M[2:0] GP1M[2:0] IEN 000000000 000000000 not reset 001010101 000000101 0 001010000 001010101 0 001010000 001010101 0 001010000 001010101 001111001 001111001 001111001 001111001 001111001 OUT3SW[1:0] 000000000 0 3DLC MICB PGAL ROUT2 0 0 GPIO5 VDAC PGAR OUT3 0 RDDAT GPIO4 GPIO3 0 IPOL MICDET IPOL MICSHT 000000000 0 0 ADCDIV2 DACDIV2 TOEN 3DEN 0 RXMIX MONO2 DIGENB LINEMIX 0 LEFTMIX READEN MICDET MICSHT 000000000 0 0 LDACVOL[7:0] RDACVOL[7:0] BASS[3:0] TRBL[3:0] ALCL[3:0] HLD[3:0] ATK[3:0] NGG NGAT 011111111 011111111 000001111 000001111 001111011 000000000 000110010 000000000 011000011 011000011 011000000 000000000 000000000 000000000 000000000 000000000 000000000 PBMODE[2:0] BMODE[2:0] VXDOSR ADCOSR DACOSR 000000111 Interface Control Sample Rate Ctrl SRMODE PSR 0 SR[4:0] USB 000000000 0 VXCLKTRI BCLKTRI VXDTRI ADCDTRI IFMODE[1:0] VXFSOE LRCOE 000110011 0 BCLKINV MS LRSWAP LRP WL[1:0] FORMAT[1:0] 000001010 DAC Control ADC Control PCM Audio ADCDOP VXCLKIN PMS MONO PLRP PWL[1:0] PFORMAT[1:0] 000001010 0 0 DACINV DMONOMIX[1:0] VXFILT DACMU DEEMPH[1:0] HPOR 0 ADCHPD 000001000 000000000 REMARKS BIT[8] BIT[7] BIT[6] BIT[5] BIT[4] BIT[3] BIT[2] BIT[1] BIT[0] DEFAULT
DATSEL[1:0]
ADCPOL[1:0]
HPMODE[1:0]
ALCSEL[1:0] ALCZC 0 0 LAVU RAVU 0 0
3DDEPTH[3:0] DACL ADCL OUT4 RECMIX DACR ADCR MONO1
VMIDSEL[1:0] MICAMP1EN MICAMP2E LOUT1 0 0 ROUT1 0 0
MONOMIX RIGHTMIX READSEL[2:0]
writing 000000000 to this register resets all registers to their default state RSEL 0 LM2LO ST2LO RM2RO ST2RO MM2MO ST2MO LO1ZC RO1ZC LO2ZC RO2ZC MOZC HPSWEN HPSWPO TSDEN 0 RRECVOL[2:0] 0 LM2LOVOL[2:0] ST2LOVOL[2:0] RM2ROVOL[2:0] ST2ROVOL[2:0] MM2MOVOL[2:0] ST2MOVOL[2:0] 0 LSEL MSEL 0 0 0 0 0 VXD2MO LOUT1VOL[6:0] ROUT1VOL[6:0] LOUT2VOL[6:0] ROUT2VOL[6:0] MONO2VOL[6:0] VROI ROUT2INV 0 0 0 LRECVOL[2:0] MRECVOL[2:0] 0 VXD2LOVOL[2:0] 0 VXD2ROVOL[2:0] 0 VXD2MOVOL[2:0]
MONO2SW[1:0]
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WM8753L
R46 (2Eh) R47 (2Fh) R48 (30h) R49 (31h) R50 (32h) R51 (33h) 0101110 0101111 0110000 0110001 0110010 0110011 ADC input mode Input Control (1) Input Control (2) Left Input volume Right Input volume Mic Bias comp control Clock Control 0 PCMDIV[2:0] SLWCLK MCLK SEL 0 0 CLK1SEL CLK1 DIV2 PLL1N[3:0] 0 PLL1K [17:9] PLL1K [8:0] 0 0 0 CLK2SEL CLK2 DIV2 R58 (3Ah) R59 (3Bh) R60 (3Ch) R61 (3Dh) 0111010 0111011 0111100 0111101 PLL2 Control (2) PLL2 Control (3) PLL2 Control (4) Bias control VDACBIAS X0P5 R63 (3Fh) 0111111 Additional Control MBIAS BOOST TSADEN 0 0 0 MICBIASBOOST[1:0] PLL2N[3:0] 0 PLL2K [17:9] PLL2K [8:0] BUFBIAS[1:0] IPBIAS X0P5 0 OPBIAS X0P5 MCLK2 DIV2 PLL2 DIV2 PLL2K [21:18] PLL2RB PCM CLKSEL MCLK1 DIV2 PLL1 DIV2 PLL1K [21:18] PLL1RB CLKEQ 0 0 0 MONOMIX[1:0] RADCSEL[1:0] MM MIC2ALC MIC2BOOST[1:0] 0 LIVU RIVU MBVSEL MIC1BOOST[1:0] LMSEL[1:0] LINEALC RM
Advanced Information
LADCSEL[1:0] LM RXALC 000000000 000000000 000000000 010010111 010010111 MBCEN 000000000 GP1CLK1SEL GP2CLK2SEL 000000100 PLL1EN 000000000 100000011 000100100 110111010 PLL2EN 000000000 100000011 000100100 110111010 ADCBIAS[1:0] 000000000 OUT4SW[1:0] DMBIAS XOP5 000000000
RXMSEL[1:0] LINMUTE RINMUTE LIZC RIZC
MICMUX[1:0]
MIC1ALC
LINVOL[5:0] RINVOL[5:0] MBSCTHRESH[1:0] MBTHRESH[2:0]
MICSEL[1:0]
R52 (34h)
0110100
R53 (35h) R54 (36h) R55 (37h) R56 (38h) R57 (39h)
0110101 0110110 0110111 0111000 0111001
PLL1 Control (1) PLL1 Control (2) PLL1 Control (3) PLL1 Control (4) PLL2 Control (1)
Table 73 Complete Register Map
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Advanced Information
WM8753L
The ADC and DAC employ different digital filters. There are 4 types of digital filter, called Type 0, 1, 2 and 3. The performance of Types 0 and 1 is listed in the table below, the responses of all filters is shown in the proceeding pages.
DIGITAL FILTER CHARACTERISTICS
PARAMETER Passband Passband Ripple Stopband Stopband Attenuation Group Delay
TEST CONDITIONS +/- 0.05dB -6dB
MIN 0
TYP
MAX 0.416fs
UNIT
ADC Filter Type 0 (USB Mode, 250fs operation) 0.5fs +/- 0.05 0.584fs f > 0.584fs -60 17/fs +/- 0.05dB -6dB Passband Ripple Stopband Stopband Attenuation Group Delay ADC High Pass Filter High Pass Frequency Filter Corner -3dB -0.5dB -0.1dB DAC Filter Type 0 (USB mode, 250fs operation) Passband Passband Ripple Stopband Stopband Attenuation Group Delay DAC Filter Type 1 (USB mode, 272fs or Normal mode operation) Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 74 HiFi Digital Filter Characteristics f > 0.5465fs 0.5465fs -50 18/fs dB +/- 0.03dB -6dB 0 0.5fs +/- 0.03 dB 0.4535fs f > 0.584fs 0.584fs -50 15/fs dB +/- 0.03dB -6dB 0 0.5fs +/-0.03 dB 0.416fs 3.7 10.4 21.6 Hz f > 0.5465fs 0.5465fs -60 25/fs dB 0 0.5fs +/- 0.05 dB 0.4535fs dB dB
ADC Filter Type 1 (USB mode, 272fs or Normal mode operation) Passband
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WM8753L
PARAMETER Voice ADC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Voice DAC Filter Passband Passband Ripple Stopband Stopband Attenuation Group Delay Table 75 Voice Codec Digital Filter Characteristics PARAMETER High Pass Filter Corner Frequency TEST CONDITIONS -3dB -0.5dB -0.1dB ADC High Pass Filter (HPMODE[1:0] = 01) (256fs, fs=16kHz) High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB ADC High Pass Filter (HPMODE[1:0] = 10) (256fs, fs=8kHz) High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB ADC High Pass Filter (HPMODE[1:0] = 11) (256fs, fs=8kHz) High Pass Filter Corner Frequency -3dB -0.5dB -0.1dB Table 76 ADC Highpass Filter Characteristics 170 321 415 82 185 272 82 203 341 MIN TYP 3.7 10.4 21.6 MAX f > 0.53fs 0.53fs -30 7/fs +/- 0.3dB -14dB 0 0.5fs +/-0.3 0.414fs f > 0.53fs 0.53fs -30 7/fs +/- 0.3dB -14dB 0 0.5fs +/- 0.3 0.414fs TEST CONDITIONS MIN TYP MAX
Advanced Information
UNIT
dB dB
dB dB
UNIT Hz
ADC High Pass Filter (HPMODE[1:0] = 00) (256fs, fs=48kHz)
Hz
Hz
Hz
TERMINOLOGY
1. 2. Stop Band Attenuation (dB) - the degree to which the frequency spectrum is attenuated (outside audio band) Pass-band Ripple - any variation of the frequency response in the pass-band region
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Advanced Information
WM8753L
0.02
DAC FILTER RESPONSES
0
0.01
-20
0
Response (dB)
-40
Response (dB)
0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.01 -0.02 -0.03 -0.04 -0.05
-60
-80
-100
-0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 28 DAC Digital Filter Frequency Response - Type 0
0
Figure 29 DAC Digital Filter Ripple - Type 0
0.02 0.01
-20
0
Response (dB)
-40
Response (dB)
-0.01 -0.02 -0.03 -0.04
-60
-80
-0.05
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 30 DAC Digital Filter Frequency Response - Type 1
Figure 31 DAC Digital Filter Ripple - Type 1
0.02
0
0.01
-20
0
Response (dB)
-40
Response (dB)
-0.01 -0.02 -0.03 -0.04
-60
-80
-0.05
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.06 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 32 DAC Digital Filter Frequency Response - Type 2
Figure 33 DAC Digital Filter Ripple - Type 2
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0.25
0
Advanced Information
0.2
-20
0.15 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-0.15 -0.2
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 34 DAC Digital Filter Frequency Response - Type 3 Figure 35 DAC Digital Filter Ripple - Type 3
ADC FILTER RESPONSES
0.04
0
0.03
-20
0.02
Response (dB)
-40
Response (dB)
0.01 0 -0.01 -0.02
-60
-80
-0.03
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.04 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 36 ADC Digital Filter Frequency Response - Type 0
0
Figure 37 ADC Digital Filter Ripple - Type 0
0.02 0.01
-20
0
Response (dB)
-40
Response (dB)
-0.01 -0.02 -0.03 -0.04
-60
-80
-0.05
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.06 0 0.05 0.1 0.15 0.2 0.25 0.3 Frequency (Fs) 0.35 0.4 0.45 0.5
Figure 38 ADC Digital Filter Frequency Response - Type 1
Figure 39 ADC Digital Filter Ripple - Type 1
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Advanced Information
0.25
0
WM8753L
0.2
-20
0.15 0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-0.15 -0.2
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 40 ADC Digital Filter Frequency Response - Type 2
Figure 41 ADC Digital Filter Ripple - Type 2
0.25
0
0.2 0.15
-20
0.1
Response (dB)
Response (dB)
-40
0.05 0 -0.05 -0.1
-60
-80
-0.15 -0.2
-100 0 0.5 1 1.5 Frequency (Fs) 2 2.5 3
-0.25 0 0.05 0.1 0.15 Frequency (Fs) 0.2 0.25
Figure 42 ADC Digital Filter Frequency Response - Type 3 Figure 43 ADC Digital Filter Ripple - Type 3
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WM8753L VOICE FILTER RESPONSES
VOICE DAC FILTER RESPONSES
10 0 -10
Response (dB) 2 0 -2 -4 -6 -8 -10 -12 -14 -16 0 0.1 0.2 Frequency (Fs) 0.3 0.4
Advanced Information
Response (dB)
-20 -30 -40 -50 -60 -70 -80 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs)
0.5
Figure 44 Voice DAC Digital Filter Frequency Response
Figure 45 Voice DAC Digital Filter Frequency Response
0.4 0.3 0.2 Response (dB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 46 Voice DAC Digital Filter Ripple
VOICE ADC FILTER RESPONSES
10 0 -10
Response (dB)
2 0 -2 -4 -6 -8 -10 -12 -14 -16 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Response (dB)
-20 -30 -40 -50 -60 -70 -80 0 0.5 1 1.5 2 2.5 3 3.5 4 Frequency (Fs)
Figure 47 Voice ADC Digital Filter Frequency Response
Figure 48 Voice ADC Digital Filter Frequency Response
0.4 0.3 0.2 Response (dB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 0 0.1 0.2 Frequency (Fs) 0.3 0.4 0.5
Figure 49 Voice ADC Digital Filter Ripple
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Advanced Information
WM8753L
DE-EMPHASIS FILTER RESPONSES
0
0.4 0.3
-2
0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8
-0.3
-10 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000
-0.4 0 2000 4000 6000 8000 10000 Frequency (Fs) 12000 14000 16000
Figure 50 De-emphasis Frequency Response (32kHz)
0
Figure 51 De-emphasis Error (32kHz)
0.4 0.3
-2
0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8
-0.3 -0.4
-10 0 5000 10000 Frequency (Fs) 15000 20000
0
5000
10000 Frequency (Fs)
15000
20000
Figure 52 De-emphasis Frequency Response (44.1kHz)
0
Figure 53 De-emphasis Error (44.1kHz)
0.4 0.3
-2
0.2
Response (dB)
-4
Response (dB)
0.1 0 -0.1 -0.2
-6
-8
-0.3 -0.4
-10 0 5000 10000 Frequency (Fs) 15000 20000
0
5000
10000 Frequency (Fs)
15000
20000
Figure 54 De-emphasis Frequency Response (48kHz)
Figure 55 De-emphasis Error (48kHz)
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WM8753L HIGHPASS FILTER
The WM8753 has a selectable digital highpass filter in the ADC filter path to remove DC offsets. HPMODE[1:0] = 00 The filter response is characterised by the following polynomial: H(z) = 1 - z-1 1 - 0.9995z-1
Advanced Information
5
0
Response (dB)
-5
-10
-15 0.0000
0.0005
0.0010 Frequency (Fs)
0.0015
0.0020
Figure 56 ADC Highpass Filter Response, HPMODE[1:0] = 00
HPMODE[1:0] = 01 The filter response is characterised by the following polynomial: H(z) = 1 - z-1 1 - 0.96875z-1
5
0
-5 Response (dB)
-10
-15
-20
-25 0.00
0.01
0.02
0.03
0.04
0.05
Fre quency (Fs)
Figure 57 ADC Highpass Filter Response, HPMODE[1:0] = 01
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Advanced Information HPMODE[1:0] = 10 The filter response is characterised by the following polynomial: H(z) = 1 - z-1 1 - 0.9375z-1
5
WM8753L
0
-5 Response (dB)
-10
-15
-20
-25
-30 0.00
0.01
0.02
0.03
0.04
0.05
Frequency (Fs)
Figure 58 ADC Highpass Filter Response, HPMODE[1:0] = 10
HPMODE[1:0] = 11 The filter response is characterised by the following polynomial: H(z) = 1 - z-1 1 - 0.875z-1
5
0
-5 Response (dB)
-10
-15
-20
-25
-30 0.00
0.01
0.02
0.03
0.04
0.05
0.06
0.07
0.08
0.09
0.10
Freque ncy (Fs)
Figure 59 ADC Highpass Filter Response, HPMODE[1:0] = 11
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WM8753L PACKAGE DIAGRAM - 48-PIN QFN
FL: 48 PIN QFN PLASTIC PACKAGE 7 X 7 X 0.9 mm BODY, 0.50 mm LEAD PITCH
D2 D2/2 37 48 L 36 1 INDEX AREA (D/2 X E/2)
Advanced Information
DM029.C
SEE DETAIL 1
D
E2/2
E2 SEE DETAIL 2
E
25
12 2X b 2X aaa C aaa C
24 e
13
TOP VIEW
ccc C (A3) A 0.08 C
C
SEATING PLANE
A1
DETAIL 1
DETAIL 2
1
DETAIL 3
W T (A3) H b Exposed lead G 0.35mm 45 degrees
Datum
Terminal tip e/2
e R
Half etch tie bar
DETAIL 3
Symbols A A1 A3 b D D2 E E2 e G H L T W aaa bbb ccc REF
Dimensions (mm) NOM MAX 0.90 1.00 0.05 0.02 0.20 REF 0.18 0.25 0.30 7.00 BSC 5.00 5.15 5.25 7.00 BSC 5.00 5.15 5.25 0.5 BSC 0.213 0.1 0.50 0.30 0.4 0.1 0.2 Tolerances of Form and Position 0.15 0.10 0.10 MIN 0.80 0
NOTE
1
JEDEC, MO-220, VARIATION VKKD-2
NOTES: 1. DIMENSION b APPLIED TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.15 mm AND 0.30 mm FROM TERMINAL TIP. 2. ALL DIMENSIONS ARE IN MILLIMETRES 3. THE TERMINAL #1 IDENTIFIER AND TERMINAL NUMBERING CONVENTION SHALL CONFORM TO JESD 95-1 SPP-002. 4. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS. 5. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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Advanced Information
WM8753L
PACKAGE DIAGRAM - 52-PIN BGA
B: 52 BALL BGA PLASTIC PACKAGE 5 X 5 X 0.9 mm BODY, 0.50 mm BALL PITCH
5 D 2 A A2 A B C D e E F G H J 2X e 0.10 Z 0.10 Z 6 E1 E
DM034.A
DETAIL 1
9 8 7 6 5 4 3 2 1 4 A1 CORNER
DETAIL 2
D1
2X
TOP VIEW
BOTTOM VIEW
SOLDER BALL
bbb Z aaa Z 1 b A1 3
Z
DETAIL 2
DETAIL 1
ccc Z X Y ddd Z
Symbols A A1 A2 b D D1 E E1 e aaa bbb ccc ddd MIN 0.95 0.15 0.80 0.25 NOM 1.11 0.21 0.90 0.30
Dimensions (mm) MAX NOTE 1.27 0.27 1.00 0.35
5.00 BSC 4.00 BSC 5.00 BSC 4.00 BSC 0.50 BSC Tolerances of Form and Position 0.80 0.10 0.15 0.05
6
NOTES: 1. PRIMARY DATUM -Z- AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS. 2. THIS DIMENSION INCLUDES STAND-OFF HEIGHT `A1'. 3. DIMENSION `b' IS MEASURED AT THE MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM -Z-. 4. A1 CORNER IS IDENTIFIED BY INK/LASER MARK ON TOP PACKAGE. 5. BILATERAL TOLERANCE ZONE IS APPLIED TO EACH SIDE OF THE PACKAGE BODY. 6. `e' REPRESENTS THE BASIC SOLDER BALL GRID PITCH. 7. THIS DRAWING IS SUBJECT TO CHANGE WITHOUT NOTICE.
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WM8753L IMPORTANT NOTICE
Advanced Information
Wolfson Microelectronics plc (WM) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current. All products are sold subject to the WM terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability. WM warrants performance of its products to the specifications applicable at the time of sale in accordance with WM's standard warranty. Testing and other quality control techniques are utilised to the extent WM deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. In order to minimise risks associated with customer applications, adequate design and operating safeguards must be used by the customer to minimise inherent or procedural hazards. Wolfson products are not authorised for use as critical components in life support devices or systems without the express written approval of an officer of the company. Life support devices or systems are devices or systems that are intended for surgical implant into the body, or support or sustain life, and whose failure to perform when properly used in accordance with instructions for use provided, can be reasonably expected to result in a significant injury to the user. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. WM assumes no liability for applications assistance or customer product design. WM does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of WM covering or relating to any combination, machine, or process in which such products or services might be or are used. WM's publication of information regarding any third party's products or services does not constitute WM's approval, license, warranty or endorsement thereof. Reproduction of information from the WM web site or datasheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations and notices. Representation or reproduction of this information with alteration voids all warranties provided for an associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use. Resale of WM's products or services with statements different from or beyond the parameters stated by WM for that product or service voids all express and any implied warranties for the associated WM product or service, is an unfair and deceptive business practice, and WM is not responsible nor liable for any such use.
ADDRESS:
Wolfson Microelectronics plc Westfield House 26 Westfield Road Edinburgh EH11 2QB United Kingdom Tel :: +44 (0)131 272 7000 Fax :: +44 (0)131 272 7001 Email :: sales@wolfsonmicro.com
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